diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-09-21 11:13:33 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-24 09:16:58 +0000 |
| commit | 0542741e0e8727ae53bce47a1fd4459735056b53 (patch) | |
| tree | 9763cda3eda742134912a49105aaf492622c24ee /chip/mt8192_scp | |
| parent | 1c3c2140f333f4a169f047fad8a780d0b71c2e5d (diff) | |
| download | chrome-ec-0542741e0e8727ae53bce47a1fd4459735056b53.tar.gz | |
it83xx: read_clear_int_mask() read and clear interrupt bit.
This change pulled the operation of interrupt disable into
read_clear_int_mask().
Because riscv core supports instruction csrrc to atomic read and
clear bit in CSR register. With this change, we won't need to separate
operations of reading and clearing interrupt bit on riscv core.
BUG=none
BRANCH=none
TEST=read_clear_int_mask() is able to disable interrupt and return
saved interrupt bit on both nds32 and riscv cores.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/mt8192_scp')
| -rw-r--r-- | chip/mt8192_scp/ipi.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/chip/mt8192_scp/ipi.c b/chip/mt8192_scp/ipi.c index 83d9fa8ebb..4081e47075 100644 --- a/chip/mt8192_scp/ipi.c +++ b/chip/mt8192_scp/ipi.c @@ -30,10 +30,8 @@ static uint32_t disable_irq_count, saved_int_mask; void ipi_disable_irq(void) { - if (atomic_inc(&disable_irq_count, 1) == 0) { - saved_int_mask = get_int_mask(); - interrupt_disable(); - } + if (atomic_inc(&disable_irq_count, 1) == 0) + saved_int_mask = read_clear_int_mask(); } void ipi_enable_irq(void) |