ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 140 deletions

diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h
deleted file mode 100644
index 13e5ad1a42..0000000000
--- a/chip/mt_scp/rv32i_common/cache.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CACHE_H
-#define __CROS_EC_CACHE_H
-
-#include "common.h"
-#include "csr.h"
-#include "stdint.h"
-#include "util.h"
-
-/* rs1 0~31 register X0~X31 */
-#define COP(rs1) (((rs1) << 15) | 0x400f)
-
-#define COP_OP_BARRIER_ICACHE		0x0
-#define COP_OP_INVALIDATE_ICACHE	0x8
-#define COP_OP_INVALIDATE_ICACHE_ADDR	0x9
-
-#define COP_OP_BARRIER_DCACHE		0x10
-#define COP_OP_WRITEBACK_DCACHE		0x14
-#define COP_OP_WRITEBACK_DCACHE_ADDR	0x15
-#define COP_OP_INVALIDATE_DCACHE	0x18
-#define COP_OP_INVALIDATE_DCACHE_ADDR	0x19
-/* FLUSH = WRITEBACK + INVALIDATE */
-#define COP_OP_FLUSH_DCACHE		0x1C
-#define COP_OP_FLUSH_DCACHE_ADDR	0x1D
-
-static inline void cache_op_all(uint32_t op)
-{
-	register int t0 asm("t0") = op;
-	asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-}
-
-static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
-{
-	size_t offset;
-	register int t0 asm("t0");
-
-	/* NOTE: cache operations must use 32 byte aligned address */
-	if (addr & GENMASK(3, 0))
-		return EC_ERROR_INVAL;
-
-	for (offset = 0; offset < length; offset += 4) {
-		t0 = addr + offset + op;
-		asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-	}
-
-	return EC_SUCCESS;
-}
-
-/* memory barrier of I$ */
-static inline void cache_barrier_icache(void)
-{
-	cache_op_all(COP_OP_BARRIER_ICACHE);
-}
-
-/* invalidate all I$ */
-static inline void cache_invalidate_icache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_ICACHE);
-}
-
-/* invalidate a range of I$ */
-static inline int cache_invalidate_icache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR);
-}
-
-/* memory barrier of D$ */
-static inline void cache_barrier_dcache(void)
-{
-	cache_op_all(COP_OP_BARRIER_DCACHE);
-}
-
-/* writeback all D$ */
-static inline void cache_writeback_dcache(void)
-{
-	cache_op_all(COP_OP_WRITEBACK_DCACHE);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-}
-
-/* writeback a range of D$ */
-static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length)
-{
-	int ret = cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-	return ret;
-}
-
-/* invalidate all D$ */
-static inline void cache_invalidate_dcache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_DCACHE);
-}
-
-/* invalidate a range of D$ */
-static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR);
-}
-
-/* writeback and invalidate all D$ */
-static inline void cache_flush_dcache(void)
-{
-	cache_op_all(COP_OP_FLUSH_DCACHE);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-}
-
-/* writeback and invalidate a range of D$ */
-static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length)
-{
-	int ret = cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR);
-	cache_barrier_icache();
-	cache_barrier_dcache();
-	return ret;
-}
-
-struct mpu_entry {
-	/* 1k alignment and the address is inclusive */
-	uintptr_t start_addr;
-	/* 1k alignment in 4GB boundary and non-inclusive */
-	uintptr_t end_addr;
-	/* MPU_ATTR */
-	uint32_t attribute;
-};
-
-void cache_init(void);
-
-#ifdef DEBUG
-int command_enable_pmu(int argc, char **argv);
-int command_disable_pmu(int argc, char **argv);
-int command_show_pmu(int argc, char **argv);
-#endif
-
-#endif /* #ifndef __CROS_EC_CACHE_H */