ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 82 deletions

diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h
deleted file mode 100644
index 434caba1d8..0000000000
--- a/chip/npcx/config_chip-npcx5.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_CONFIG_CHIP_NPCX5_H
-#define __CROS_EC_CONFIG_CHIP_NPCX5_H
-
-/*
- * NPCX5 Series Device-Specific Information
- * Ex. NPCX5(M)(N)(G)
- * @param M: 7: 132-pins package, 8: 128-pins package
- * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size
- * @param G: Google EC.
- */
-
-/* Chip ID for all variants */
-#define NPCX585G_CHIP_ID		0x12
-#define NPCX575G_CHIP_ID		0x13
-#define NPCX586G_CHIP_ID		0x16
-#define NPCX576G_CHIP_ID		0x17
-
-/*****************************************************************************/
-/* Hardware features */
-
-/* Number of UART modules. */
-#define UART_MODULE_COUNT 1
-
-/*
- * For NPCX5, PS2_3 pins also support other alternate functions (e.g., TA2).
- * PS2_3 should be Explicit defined.
- */
-#undef NPCX_PS2_MODULE_3
-
-/*
- * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
- * additional port.
- */
-#define CONFIG_I2C_MULTI_PORT_CONTROLLER
-/* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT	4
-/* Number of I2C ports */
-#define I2C_PORT_COUNT		5
-
-/*****************************************************************************/
-/* Memory mapping */
-#define NPCX_BTRAM_SIZE		0x800 /* 2KB data ram used by booter. */
-#define CONFIG_RAM_BASE		0x200C0000 /* memory address of data ram */
-#define CONFIG_DATA_RAM_SIZE	0x00008000 /* Size of data RAM */
-#define CONFIG_RAM_SIZE		(CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-#define CONFIG_LPRAM_BASE	0x40001600 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
-
-/* Use chip variant to specify the size and start address of program memory */
-#if defined(CHIP_VARIANT_NPCX5M5G)
-/* 96KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024)
-/* program memory base address for 96KB Code RAM (ie. 0x100C0000 - 96KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-/* 224KB RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024)
-/* program memory base address for 224KB Code RAM (ie. 0x100C0000 - 224KB) */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000
-#else
-#error "Unsupported chip variant"
-#endif
-
-/* Total RAM size checking for npcx ec */
-#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
-#if defined(CHIP_VARIANT_NPCX5M5G)
-/* 128KB RAM in NPCX5M5G */
-#if (NPCX_RAM_SIZE != 0x20000)
-#error "Wrong memory mapping layout for NPCX5M5G"
-#endif
-#elif defined(CHIP_VARIANT_NPCX5M6G)
-/* 256KB RAM in NPCX5M6G */
-#if (NPCX_RAM_SIZE != 0x40000)
-#error "Wrong memory mapping layout for NPCX5M6G"
-#endif
-#endif
-
-#endif /* __CROS_EC_CONFIG_CHIP_NPCX5_H */