diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2018-04-13 16:08:23 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-04-18 02:08:10 -0700 |
| commit | 6f8c010eb587dd1f017ff369a6e645913205a3a7 (patch) | |
| tree | ab2874f29e4d0b642a292d42362be1df2d657524 /chip/npcx/config_chip-npcx7.h | |
| parent | dcaf8edc47c1703a760eff4d9ea12f68f8af492c (diff) | |
| download | chrome-ec-6f8c010eb587dd1f017ff369a6e645913205a3a7.tar.gz | |
npcx7: uart: Add FIFO mode support
NPCX79nxB chips add UART FIFO support with 16-bytes of TX/RX buffers.
This CL enables the UART FIFO mode when NPCX79nxB chips are used.
The UART interrupt priority is decreased from 1 to 4 because now it has
the capability to buffter data in the FIFO when ec is serving the
interrupts with higher priority.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=stress test the uart port by shell command "while true; do echo
'taskinfo'>/dev/pts/19; sleep 0.1; done".
Change-Id: Ib09c1b5550d0db249201fc4fdd8d3b28c24b8a8e
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1012002
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip-npcx7.h')
| -rw-r--r-- | chip/npcx/config_chip-npcx7.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index d2cf002ee2..74a4c30c36 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -25,6 +25,10 @@ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #endif +#if defined(CHIP_VARIANT_NPCX7M7W) || defined(CHIP_VARIANT_NPCX7M6XB) +#define NPCX_UART_FIFO_SUPPORT +#endif + #ifdef CHIP_VARIANT_NPCX7M7W #define NPCX_WOV_SUPPORT /* Audio front-end for Wake-on-Voice support */ #endif |