chip/npcx/espi: Handle global reset events asserting eSPI_Reset#

In case there is a sudden power loss to PCH, then there are no eSPI VW
messages sent from the PCH to EC indicating power state transition into
S5. Instead, the eSPI compatibility spec defines such events as global
reset events. For global reset events, eSPI_Reset# signal is asserted
without SLP_SUS# being asserted. This acts as an indication to the EC
that there was a global reset event.

Add a callback chipset_handle_espi_reset_assert that takes any necessary
action whenever eSPI_Reset# pin is asserted. On skylake, it would check
if power button was being pressed and release the button.

BUG=chrome-os-partner:62014
BRANCH=None
TEST=Verified that apshutdown works as expected.

Change-Id: I409afa0d00faca55ae3aa577743cedac58d4d877
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438935
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 41d61484a4..16cfe441e0 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -8,6 +8,7 @@
 #include "registers.h"
 #include "system.h"
 #include "task.h"
+#include "chipset.h"
 #include "console.h"
 #include "uart.h"
 #include "util.h"
@@ -542,6 +543,7 @@ void espi_interrupt(void)
 		} /* eSPI reset (from eSPI_rst pin) */
 		else if (IS_BIT_SET(status, NPCX_ESPISTS_ESPIRST)) {
 			CPRINTS("eSPI RST");
+			chipset_handle_espi_reset_assert();
 			espi_reset_recovery();
 		}