diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2017-02-04 11:58:16 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-13 18:25:51 -0800 |
| commit | 1a736ed9542eb4c94ab0a49dba7696cda7faf864 (patch) | |
| tree | 57d7a29b781f9afb33cd3da59983571096d74165 /chip/npcx/flash.c | |
| parent | f51fdf223dd846341a489b00c8f43db92a37ce37 (diff) | |
| download | chrome-ec-1a736ed9542eb4c94ab0a49dba7696cda7faf864.tar.gz | |
kevin / gru: Reduce SRAM footprint
Remove console commands and add CONFIG options to reduce RAM usage.
BUG=chrome-os-partner:54099
BRANCH=gru
TEST=Verify charge_ramp CONFIG + task builds for gru.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I2d7bc77d1fc032c6cb75eb1ec8d13dacb676658d
Reviewed-on: https://chromium-review.googlesource.com/437662
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip/npcx/flash.c')
| -rw-r--r-- | chip/npcx/flash.c | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index 6d54b61126..4921e5200f 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -58,12 +58,6 @@ static void flash_pinmux(int enable) } } -static void flash_tristate(int enable) -{ - /* Enable/Disable FIU pins to tri-state */ - UPDATE_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS, enable); -} - static void flash_execute_cmd(uint8_t code, uint8_t cts) { /* set UMA_CODE */ @@ -369,16 +363,6 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes, return rv; } -static int flash_spi_sel_lock(int enable) -{ - /* - * F_SPI_QUAD, F_SPI_CS1_1/2, F_SPI_TRIS become read-only - * if this bit is set - */ - UPDATE_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK, enable); - return IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK); -} - /*****************************************************************************/ int flash_physical_read(int offset, int size, char *data) @@ -672,6 +656,23 @@ DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, #endif +#ifdef CONFIG_CMD_FLASH_TRISTATE +static void flash_tristate(int enable) +{ + /* Enable/Disable FIU pins to tri-state */ + UPDATE_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS, enable); +} + +static int flash_spi_sel_lock(int enable) +{ + /* + * F_SPI_QUAD, F_SPI_CS1_1/2, F_SPI_TRIS become read-only + * if this bit is set + */ + UPDATE_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK, enable); + return IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_F_SPI_SLLK); +} + /*****************************************************************************/ /* Console commands */ @@ -707,4 +708,4 @@ static int command_flash_tristate(int argc, char **argv) DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, "[0 | 1]", "Tristate spi flash pins"); - +#endif /* CONFIG_CMD_FLASH_TRISTATE */ |