diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2016-06-30 15:14:10 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-30 23:11:01 -0700 |
| commit | 5406a56269ed9ac07ff7b279f52f390fe7d14e63 (patch) | |
| tree | 353482ec3df884e442e15b246557219e2b923e02 /chip/npcx/lpc.c | |
| parent | f6b26dee24f4a4006e1a5509031972f8c0b5e9fc (diff) | |
| download | chrome-ec-stabilize-8530.35.B.tar.gz | |
npcx: deprecate use of PC87570 mode on PM chan 1stabilize-8530.Bstabilize-8530.96.Bstabilize-8530.93.Bstabilize-8530.89.Bstabilize-8530.80.Bstabilize-8530.77.Bstabilize-8530.71.Bstabilize-8530.35.Brelease-R53-8530.B
In NPCX5m5g/NPCX5m6g, PM channel 1 can support both
PC87570-Compatible and enhcnced mode. In next generation of chip,
only enhanced mode will be supported. Set the enhanced mode as
default in the firmware to support all gereration of chips.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Change-Id: Ide9e17a1fe8a0d2bfdc33efe2336a10702660679
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/357752
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Diffstat (limited to 'chip/npcx/lpc.c')
| -rw-r--r-- | chip/npcx/lpc.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index e29ed6c57b..f1c0dbde33 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -840,14 +840,18 @@ static void lpc_init(void) /* * Init KBC - * Clear OBF status flag, PM1 IBF/OBE INT enable, IRQ11 enable, + * Clear OBF status flag, * IBF(K&M) INT enable, OBE(K&M) empty INT enable , * OBF Mouse Full INT enable and OBF KB Full INT enable */ - NPCX_HICTRL = 0xFF; - - /* Normally Polarity IRQ1,12,11 type (level + high) setting */ - NPCX_HIIRQC = 0x00; /* Make sure to default */ + NPCX_HICTRL = 0x8F; + /* + * Turn on enhance mode on PM channel-1, + * enable OBE/IBF core interrupt + */ + NPCX_HIPMCTL(PMC_ACPI) |= 0x83; + /* Normally Polarity IRQ1,12 type (level + high) setting */ + NPCX_HIIRQC = 0x04; /* * Init PORT80 |