ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 103 deletions

diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
deleted file mode 100644
index e3cc2a8865..0000000000
--- a/chip/npcx/system_chip.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NPCX-specific SIB module for Chrome EC */
-
-#ifndef __CROS_EC_SYSTEM_CHIP_H
-#define __CROS_EC_SYSTEM_CHIP_H
-
-/* Flags for BBRM_DATA_INDEX_WAKE */
-#define HIBERNATE_WAKE_MTC        BIT(0)  /* MTC alarm */
-#define HIBERNATE_WAKE_PIN        BIT(1)  /* Wake pin */
-#define HIBERNATE_WAKE_LCT        BIT(2)  /* LCT alarm */
-/*
- * Indicate that EC enters hibernation via PSL. When EC wakes up from
- * hibernation and this flag is set, it will check the related status bit to
- * know the actual wake up source. (From LCT or physical wakeup pins)
- */
-#define HIBERNATE_WAKE_PSL        BIT(3)
-
-/* Indices for battery-backed ram (BBRAM) data position */
-enum bbram_data_index {
-	BBRM_DATA_INDEX_SCRATCHPAD = 0,        /* General-purpose scratchpad */
-	BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
-	BBRM_DATA_INDEX_WAKE = 8,	       /* Wake reasons for hibernate */
-	BBRM_DATA_INDEX_PD0 = 12,	       /* USB-PD saved port0 state */
-	BBRM_DATA_INDEX_PD1 = 13,	       /* USB-PD saved port1 state */
-	BBRM_DATA_INDEX_TRY_SLOT = 14,         /* Vboot EC try slot */
-	BBRM_DATA_INDEX_PD2 = 15,	       /* USB-PD saved port2 state */
-	/* Index 16-31 available for future use */
-	BBRM_DATA_INDEX_RAMLOG = 32,	       /* RAM log for Booter */
-	BBRM_DATA_INDEX_PANIC_FLAGS = 35,      /* Flag to indicate validity of
-						* panic data starting at index
-						* 36.
-						*/
-	BBRM_DATA_INDEX_PANIC_BKUP = 36,       /* Panic data (index 35-63)*/
-	BBRM_DATA_INDEX_LCT_TIME = 64,         /* The start time of LCT(4 bytes)
-						*/
-};
-
-enum psl_pin_t {
-	PSL_IN1,
-	PSL_IN2,
-	PSL_IN3,
-	PSL_IN4,
-	PSL_NONE,
-};
-
-/* Issue a watchdog reset */
-void system_watchdog_reset(void);
-
-/* Stops the watchdog timer and unlocks configuration. */
-void watchdog_stop_and_unlock(void);
-
-/*
- * Configure the specific memory addresses in the the MPU
- * (Memory Protection Unit) for Nuvoton different chip series.
- */
-void system_mpu_config(void);
-
-/* Hibernate function for different Nuvoton chip series. */
-void __hibernate_npcx_series(void);
-
-/* Check and clear BBRAM status on power-on reset */
-void system_check_bbram_on_reset(void);
-
-/* The utilities and variables depend on npcx chip family */
-#if defined(CHIP_FAMILY_NPCX5) || defined(CONFIG_WORKAROUND_FLASH_DOWNLOAD_API)
-/* Bypass for GMDA issue of ROM api utilities only on npcx5 series */
-void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr);
-
-/* Begin address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_start;
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __flash_lpfw_end;
-
-/* Begin address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_start;
-
-/* End address for little FW; defined in linker script */
-extern unsigned int __flash_lplfw_end;
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-/* Configure PSL mode setting for the wake-up pins. */
-int system_config_psl_mode(enum gpio_signal signal);
-
-/* Configure PSL pins and enter PSL mode. */
-void system_enter_psl_mode(void);
-
-/* End address for hibernate utility; defined in linker script */
-extern unsigned int __after_init_end;
-
-#endif
-
-#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-void system_set_psl_gpo(int level);
-#endif
-
-#endif /* __CROS_EC_SYSTEM_CHIP_H */