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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-03-23 18:27:22 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-03-25 20:09:52 +0000 |
| commit | 6ee7b1e34eecd585074b4aae0347ed12f632ead0 (patch) | |
| tree | ace73f958495a83b836505941318325fa71c71e7 /chip/npcx | |
| parent | 0f18989ef58a77800c1b393cf8223455f793d543 (diff) | |
| download | chrome-ec-stabilize-6915.B.tar.gz | |
ACPI: Support accessing memmap data over ACPI CMD / DATA portsstabilize-6915.B
Some platforms are unable to access the 900h-9ffh region over LPC and
must instead access memmap data through the ACPI CMD / DATA ports. To
avoid racing with data updates, disallow changes to multi-byte memmap
data while in burst mode.
Linux currently enables burst mode when accessing multi-byte data and
disables it immediately afterward, though the ACPI spec defines burst mode
in a more general way.
BUG=chrome-os-partner:38224
TEST=Manual on Samus. Undefine LPC_MEMMAP and modify asl to move memmap
data to ERAM at offset 0x20. Verify system boots cleanly and battery
status is updated immediately on plug / unplug.
BRANCH=None
Change-Id: Ib848bdb491fdfece96ad0cee7a44ba85b4a1a50b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/262072
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'chip/npcx')
| -rw-r--r-- | chip/npcx/lpc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 1622905299..79e0675ede 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -348,6 +348,16 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type) return event_mask[type]; } +void lpc_set_acpi_status_mask(uint8_t mask) +{ + /* TODO (crbug.com/p/38224): Implement */ +} + +void lpc_clear_acpi_status_mask(uint8_t mask) +{ + /* TODO (crbug.com/p/38224): Implement */ +} + int lpc_get_pltrst_asserted(void) { /* Read PLTRST status*/ |