ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

19 files changed, 0 insertions, 3013 deletions

diff --git a/chip/nrf51/bluetooth_le.c b/chip/nrf51/bluetooth_le.c
deleted file mode 100644
index 89eb117efd..0000000000
--- a/chip/nrf51/bluetooth_le.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h"
-#include "include/bluetooth_le.h"
-#include "console.h"
-#include "ppi.h"
-#include "radio.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_BLUETOOTH_LE, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
-
-static void ble2nrf_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p)
-{
-	if (ble_p->header_type_adv) {
-		radio_p->s0 = ble_p->header.adv.type & 0xf;
-		radio_p->s0 |= (ble_p->header.adv.txaddr ?
-			1 << BLE_ADV_HEADER_TXADD_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.adv.rxaddr ?
-			1 << BLE_ADV_HEADER_RXADD_SHIFT : 0);
-		radio_p->length = ble_p->header.adv.length & 0x3f; /* 6 bits */
-	} else {
-		radio_p->s0 = ble_p->header.data.llid & 0x3;
-		radio_p->s0 |= (ble_p->header.data.nesn ?
-			1 << BLE_DATA_HEADER_NESN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.sn ?
-			1 << BLE_DATA_HEADER_SN_SHIFT : 0);
-		radio_p->s0 |= (ble_p->header.data.md ?
-			1 << BLE_DATA_HEADER_MD_SHIFT : 0);
-		radio_p->length = ble_p->header.data.length & 0x1f; /* 5 bits */
-	}
-
-	if (radio_p->length > 0)
-		memcpy(radio_p->payload, ble_p->payload, radio_p->length);
-}
-
-static void nrf2ble_packet(struct ble_pdu *ble_p,
-		struct nrf51_ble_packet_t *radio_p, int type_adv)
-{
-	if (type_adv) {
-		ble_p->header_type_adv = 1;
-		ble_p->header.adv.type = radio_p->s0 & 0xf;
-		ble_p->header.adv.txaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_TXADD_SHIFT)) != 0;
-		ble_p->header.adv.rxaddr = (radio_p->s0 &
-			BIT(BLE_ADV_HEADER_RXADD_SHIFT)) != 0;
-		/* Length check? 6-37 Bytes */
-		ble_p->header.adv.length = radio_p->length;
-	} else {
-		ble_p->header_type_adv = 0;
-		ble_p->header.data.llid = radio_p->s0 & 0x3;
-		ble_p->header.data.nesn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_NESN_SHIFT)) != 0;
-		ble_p->header.data.sn = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_SN_SHIFT)) != 0;
-		ble_p->header.data.md = (radio_p->s0 &
-			BIT(BLE_DATA_HEADER_MD_SHIFT)) != 0;
-		/* Length check? 0-31 Bytes */
-		ble_p->header.data.length = radio_p->length;
-	}
-
-	if (radio_p->length > 0)
-		memcpy(ble_p->payload, radio_p->payload, radio_p->length);
-}
-
-struct ble_pdu adv_packet;
-struct nrf51_ble_packet_t on_air_packet;
-
-struct ble_pdu rcv_packet;
-
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return rv;
-	NRF51_RADIO_CRCCNF = 3 | NRF51_RADIO_CRCCNF_SKIP_ADDR; /* 3-byte CRC */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-
-	NRF51_RADIO_CRCINIT = crc_init_val;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	NRF51_RADIO_BASE0 = access_address << 8;
-	NRF51_RADIO_PREFIX0 = access_address >> 24;
-
-	if (access_address != BLE_ADV_ACCESS_ADDRESS)
-		CPRINTF("Initializing radio for data packet.\n");
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_ADV_DATA;
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_ADV_DATA;
-
-	return rv;
-
-}
-
-static struct nrf51_ble_packet_t tx_packet;
-
-static uint32_t tx_end, rsp_end;
-
-void ble_tx(struct ble_pdu *pdu)
-{
-	uint32_t timeout_time;
-
-	ble2nrf_packet(pdu, &tx_packet);
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	NRF51_RADIO_RXEN = 0;
-	NRF51_RADIO_TXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("ERROR DURING RADIO TX SETUP. TRY AGAIN.\n");
-			return;
-		}
-	}
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_END) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO DID NOT SHUT DOWN AFTER TX. "
-				"RECOMMEND REBOOT.\n");
-			return;
-		}
-	}
-	NRF51_RADIO_DISABLE = 1;
-}
-
-static struct nrf51_ble_packet_t rx_packet;
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv)
-{
-	uint32_t done;
-	uint32_t timeout_time;
-	int ppi_channel_requested;
-
-	/* Prevent illegal wait times */
-	if (timeout <= 0) {
-		NRF51_RADIO_DISABLE = 1;
-		return EC_ERROR_TIMEOUT;
-	}
-
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0;
-	/*
-	 * These shortcuts cause packet transmission 150 microseconds after
-	 * packet receive, as is the BTLE standard. See NRF51 manual:
-	 * section 17.1.12
-	 */
-	NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-			NRF51_RADIO_SHORTS_DISABLED_TXEN |
-			NRF51_RADIO_SHORTS_END_DISABLE;
-
-	/*
-	 * This creates a shortcut that marks the time
-	 * that the payload was received by the radio
-	 * in NRF51_TIMER_CC(0,1)
-	 */
-	ppi_channel_requested = NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1;
-	if (ppi_request_channel(&ppi_channel_requested) == EC_SUCCESS) {
-		NRF51_PPI_CHEN |= BIT(ppi_channel_requested);
-		NRF51_PPI_CHENSET |= BIT(ppi_channel_requested);
-	}
-
-
-	NRF51_RADIO_RXEN = 1;
-
-	timeout_time = get_time().val + RADIO_SETUP_TIMEOUT;
-	while (!NRF51_RADIO_READY) {
-		if (get_time().val > timeout_time) {
-			CPRINTF("RADIO NOT SET UP IN TIME. TIMING OUT.\n");
-			return EC_ERROR_TIMEOUT;
-		}
-	}
-
-	timeout_time = get_time().val + timeout;
-	do {
-		if (get_time().val >= timeout_time) {
-			NRF51_RADIO_DISABLE = 1;
-			return EC_ERROR_TIMEOUT;
-		}
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	rsp_end = get_time().le.lo;
-
-	if (NRF51_RADIO_CRCSTATUS == 0) {
-		CPRINTF("INVALID CRC\n");
-		return EC_ERROR_CRC;
-	}
-
-	nrf2ble_packet(pdu, &rx_packet, adv);
-
-	/*
-	 * Throw error if radio not yet disabled. Something has
-	 * gone wrong. May be in an unexpected state.
-	 */
-	if (NRF51_RADIO_DISABLED != 1)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/* Allow list handling */
-int ble_radio_clear_allow_list(void)
-{
-	NRF51_RADIO_DACNF = 0;
-	return EC_SUCCESS;
-}
-
-int ble_radio_read_allow_list_size(uint8_t *ret_size)
-{
-	int i, size = 0;
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-
-	/* Count the bits that are set */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++)
-		if (dacnf & NRF51_RADIO_DACNF_ENA(i))
-			size++;
-
-	*ret_size = size;
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t rand)
-{
-	uint32_t dacnf = NRF51_RADIO_DACNF;
-	int i;
-	uint32_t aligned;
-
-	/* Check for duplicates using ble_radio_remove_device? */
-
-	/* Find a free entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX &&
-		(dacnf & NRF51_RADIO_DACNF_ENA(i)); i++)
-		;
-
-	if (i == NRF51_RADIO_DACNF_MAX)
-		return EC_ERROR_OVERFLOW;
-
-	memcpy(&aligned, addr_ptr, 4);
-	NRF51_RADIO_DAB(i) = aligned;
-	memcpy(&aligned, addr_ptr + 4, 2);
-	NRF51_RADIO_DAP(i) = aligned;
-
-	NRF51_RADIO_DACNF = dacnf | NRF51_RADIO_DACNF_ENA(i) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0);
-
-	return EC_SUCCESS;
-}
-
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t rand)
-{
-	int i, dacnf = NRF51_RADIO_DACNF;
-
-	/* Find a matching entry */
-	for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++) {
-		uint32_t dab = NRF51_RADIO_DAB(i), dap = NRF51_RADIO_DAP(i);
-
-		if ((dacnf & NRF51_RADIO_DACNF_ENA(i)) && /* Enabled */
-		    /* Rand flag matches */
-		    (rand == ((dacnf & NRF51_RADIO_DACNF_TXADD(i)) != 0)) &&
-		    /* Address matches */
-		    (!memcmp(addr_ptr, &dab, 4)) &&
-		    (!memcmp(addr_ptr + 4, &dap, 2)))
-			break;
-	}
-
-	if (i == NRF51_RADIO_DACNF_MAX) /* Not found is successfully removed */
-		return EC_SUCCESS;
-
-	NRF51_RADIO_DACNF = dacnf & ~((NRF51_RADIO_DACNF_ENA(i)) |
-		(rand ? NRF51_RADIO_DACNF_TXADD(i) : 0));
-
-	return EC_SUCCESS;
-}
-
-
-int ble_adv_packet(struct ble_pdu *adv_packet, int chan)
-{
-	int done;
-	int rv;
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	ble_tx(adv_packet);
-
-	do {
-		done = NRF51_RADIO_END;
-	} while (!done);
-
-	tx_end = get_time().le.lo;
-
-	if (adv_packet->header.adv.type ==
-	    BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND)
-		return EC_SUCCESS;
-
-	rv = ble_rx(&rcv_packet, 16000, 1);
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Check for valid responses */
-	switch (rcv_packet.header.adv.type) {
-	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
-		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
-		/* Connections are only allowed for two types of advertising */
-		if (adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
-		    adv_packet->header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
-			return rv;
-		/* The advertising address needs to match */
-		if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
-		    &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-		/* The InitAddr needs to match for Directed advertising */
-		if (adv_packet->header.adv.type ==
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-		    memcmp(&adv_packet->payload[BLUETOOTH_ADDR_OCTETS],
-			   &rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
-			return rv;
-	break;
-	default: /* Unhandled response packet */
-		return rv;
-	break;
-	}
-
-	dump_ble_packet(&rcv_packet);
-	CPRINTF("tx_end %u Response %u\n", tx_end, rsp_end);
-
-	return rv;
-}
-
-int ble_adv_event(struct ble_pdu *adv_packet)
-{
-	int chan;
-	int rv;
-
-	for (chan = 37; chan < 40; chan++) {
-		rv = ble_adv_packet(adv_packet, chan);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	return rv;
-}
-
-static void fill_header(struct ble_pdu *adv, int type, int txaddr, int rxaddr)
-{
-	adv->header_type_adv = 1;
-	adv->header.adv.type = type;
-	adv->header.adv.txaddr = txaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.rxaddr = rxaddr ?
-		BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR;
-	adv->header.adv.length = 0;
-}
-
-static int fill_payload(uint8_t *payload, uint64_t addr, int name_length)
-{
-	uint8_t *curr;
-
-	curr = pack_adv_addr(payload, addr);
-	curr = pack_adv(curr, name_length, GAP_COMPLETE_NAME,
-		"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrs");
-	curr = pack_adv_int(curr, 2, GAP_APPEARANCE,
-			    GAP_APPEARANCE_HID_KEYBOARD);
-	curr = pack_adv_int(curr, 1, GAP_FLAGS,
-		GAP_FLAGS_LE_LIM_DISC | GAP_FLAGS_LE_NO_BR_EDR);
-	curr = pack_adv_int(curr, 2, GAP_COMP_16_BIT_UUID,
-			    GATT_SERVICE_HID_UUID);
-
-	return curr - payload;
-}
-
-static void fill_packet(struct ble_pdu *adv, uint64_t addr, int type,
-			int name_length)
-{
-	fill_header(adv, type, BLE_ADV_HEADER_RANDOM_ADDR,
-		    BLE_ADV_HEADER_PUBLIC_ADDR);
-
-	adv->header.adv.length = fill_payload(adv->payload, addr, name_length);
-}
-
-static int command_ble_adv(int argc, char **argv)
-{
-	int type, length, reps, interval;
-	uint64_t addr;
-	char *e;
-	int i;
-	int rv;
-
-	if (argc < 3 || argc > 5)
-		return EC_ERROR_PARAM_COUNT;
-
-	type = strtoi(argv[1], &e, 0);
-	if (*e || type < 0 || (type > 2 && type != 6))
-		return EC_ERROR_PARAM1;
-
-	length = strtoi(argv[2], &e, 0);
-	if (*e || length > 32)
-		return EC_ERROR_PARAM2;
-
-	if (argc >= 4) {
-		reps = strtoi(argv[3], &e, 0);
-		if (*e || reps < 0)
-			return EC_ERROR_PARAM3;
-	} else {
-		reps = 1;
-	}
-
-	if (argc >= 5) {
-		interval = strtoi(argv[4], &e, 0);
-		if (*e || interval < 0)
-			return EC_ERROR_PARAM4;
-	} else {
-		interval = 100000;
-	}
-
-	if (type == BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && length != 12) {
-		length = 12;
-		CPRINTS("type DIRECT needs to have a length of 12");
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-
-		CPRINTS("ADV @%pP", &adv_packet);
-
-	((uint32_t *)&addr)[0] = 0xA3A2A1A0 | type;
-	((uint32_t *)&addr)[1] = BLE_RANDOM_ADDR_MSBS_STATIC << 8 | 0x5A4;
-
-		fill_packet(&adv_packet, addr, type, length);
-
-	for (i = 0; i < reps; i++) {
-		ble_adv_event(&adv_packet);
-		usleep(interval);
-	}
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_adv, command_ble_adv,
-			"type len [reps] [interval = 100000 (100ms)]",
-			"Send a BLE packet of type type of length len");
-
-static int command_ble_adv_scan(int argc, char **argv)
-{
-	int chan, packets, i;
-	int addr_lsbyte;
-	char *e;
-	int rv;
-
-	if (argc < 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	chan = strtoi(argv[1], &e, 0);
-	if (*e || chan < 37 || chan > 39)
-		return EC_ERROR_PARAM1;
-
-	if (argc >= 3) {
-		packets = strtoi(argv[2], &e, 0);
-		if (*e || packets < 0)
-			return EC_ERROR_PARAM2;
-	} else {
-		packets = 1;
-	}
-
-	if (argc >= 4) {
-		addr_lsbyte = strtoi(argv[3], &e, 0);
-		if (*e || addr_lsbyte > 255)
-			return EC_ERROR_PARAM3;
-	} else {
-		addr_lsbyte = -1;
-	}
-
-	rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
-
-	/* Change channel */
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan));
-	NRF51_RADIO_DATAWHITEIV = chan;
-
-	CPRINTS("ADV Listen");
-	if (addr_lsbyte != -1)
-		CPRINTS("filtered (%x)", addr_lsbyte);
-
-	for (i = 0; i < packets; i++) {
-		rv = ble_rx(&rcv_packet, 1000000, 1);
-
-		if (rv == EC_ERROR_TIMEOUT)
-			continue;
-
-		if (addr_lsbyte == -1 || rcv_packet.payload[0] == addr_lsbyte)
-			dump_ble_packet(&rcv_packet);
-	}
-
-	rv = radio_disable();
-
-	CPRINTS("on_air payload rcvd %pP", &rx_packet);
-
-	return rv;
-}
-DECLARE_CONSOLE_COMMAND(ble_scan, command_ble_adv_scan,
-			"chan [num] [addr0]",
-			"Scan for [num] BLE packets on channel chan");
-
diff --git a/chip/nrf51/bluetooth_le.h b/chip/nrf51/bluetooth_le.h
deleted file mode 100644
index dbb3bccd6e..0000000000
--- a/chip/nrf51/bluetooth_le.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __NRF51_BLUETOOTH_LE_H
-#define __NRF51_BLUETOOTH_LE_H
-
-#include "common.h"
-#include "include/bluetooth_le.h"
-
-#define NRF51_BLE_LENGTH_BITS 8
-#define NRF51_BLE_S0_BYTES    1
-#define NRF51_BLE_S1_BITS     0 /* no s1 field */
-
-#define BLE_ACCESS_ADDRESS_BYTES 4
-#define EXTRA_RECEIVE_BYTES      0
-#define BLE_ADV_WHITEN           1
-
-#define RADIO_SETUP_TIMEOUT 1000
-
-/* Data and Advertisements have the same PCNF values */
-#define NRF51_RADIO_PCNF0_ADV_DATA \
-			NRF51_RADIO_PCNF0_VAL(NRF51_BLE_LENGTH_BITS, \
-			NRF51_BLE_S0_BYTES, \
-			NRF51_BLE_S1_BITS)
-
-#define NRF51_RADIO_PCNF1_ADV_DATA \
-			NRF51_RADIO_PCNF1_VAL(BLE_MAX_ADV_PAYLOAD_OCTETS, \
-		    EXTRA_RECEIVE_BYTES, \
-		    BLE_ACCESS_ADDRESS_BYTES - 1, \
-		    BLE_ADV_WHITEN)
-
-struct nrf51_ble_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t payload[BLE_MAX_DATA_PAYLOAD_OCTETS];
-} __packed;
-
-struct nrf51_ble_config_t {
-	uint8_t channel;
-	uint8_t address;
-	uint32_t crc_init;
-};
-
-/* Initialize the nRF51 radio for BLE */
-int ble_radio_init(uint32_t access_address, uint32_t crc_init_val);
-
-/* Transmit pdu on the radio */
-void ble_tx(struct ble_pdu *pdu);
-
-/* Receive a packet into pdu if one comes before the timeout */
-int ble_rx(struct ble_pdu *pdu, int timeout, int adv);
-
-/* Allow list handling */
-
-/* Clear the allow list */
-int ble_radio_clear_allow_list(void);
-
-/* Read the size of the allow list and assign it to ret_size */
-int ble_radio_read_allow_list_size(uint8_t *ret_size);
-
-/* Add the device with the address specified by addr_ptr and type */
-int ble_radio_add_device_to_allow_list(const uint8_t *addr_ptr, uint8_t type);
-
-/* Remove the device with the address specified by addr_ptr and type */
-int ble_radio_remove_device_from_allow_list(const uint8_t *addr_ptr,
-					    uint8_t type);
-
-#endif  /* __NRF51_BLUETOOTH_LE_H */
diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk
deleted file mode 100644
index 7a7a33d402..0000000000
--- a/chip/nrf51/build.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nRF51822 chip specific files build
-#
-
-CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
-
-chip-y+=gpio.o system.o uart.o
-chip-y+=watchdog.o ppi.o
-
-chip-$(CONFIG_BLUETOOTH_LE)+=radio.o bluetooth_le.o
-chip-$(CONFIG_BLUETOOTH_LE_RADIO_TEST)+=radio_test.o
-chip-$(CONFIG_COMMON_TIMER)+=hwtimer.o clock.o
-chip-$(CONFIG_I2C)+=i2c.o
-ifndef CONFIG_KEYBOARD_NOT_RAW
-chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
-endif
diff --git a/chip/nrf51/clock.c b/chip/nrf51/clock.c
deleted file mode 100644
index fe56140175..0000000000
--- a/chip/nrf51/clock.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Clocks and power management settings */
-
-void clock_init(void)
-{
-}
-
-int clock_get_freq(void)
-{
-	/* constant 16 MHz clock */
-	return 16000000;
-}
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
deleted file mode 100644
index f63fff0fe3..0000000000
--- a/chip/nrf51/config_chip.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m0/config_core.h"
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 1024
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 256
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 512
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-/*
- * --- chip variant settings ---
- */
-
-/* RAM mapping */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
-
-/* Flash mapping */
-#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Compute the rest of the flash params from these */
-#include "config_std_internal_flash.h"
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT 32
-
-/* Not that much RAM, set to smaller */
-#undef  CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 1024
-
-#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
-#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
-
diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c
deleted file mode 100644
index 53694b5a74..0000000000
--- a/chip/nrf51/gpio.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/*
- * For each interrupt (INT0-INT3, PORT), record which GPIO entry uses it.
- */
-
-static const struct gpio_info *gpio_ints[NRF51_GPIOTE_IN_COUNT];
-static const struct gpio_info *gpio_int_port;
-
-volatile uint32_t * const nrf51_alt_funcs[] = {
-	/* UART */
-	&NRF51_UART_PSELRTS,
-	&NRF51_UART_PSELTXD,
-	&NRF51_UART_PSELCTS,
-	&NRF51_UART_PSELRXD,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI0_PSELSCK,
-	&NRF51_SPI0_PSELMOSI,
-	&NRF51_SPI0_PSELMISO,
-	/* TWI0 (I2C) */
-	&NRF51_TWI0_PSELSCL,
-	&NRF51_TWI0_PSELSDA,
-	/* SPI1 (SPI Master) */
-	&NRF51_SPI1_PSELSCK,
-	&NRF51_SPI1_PSELMOSI,
-	&NRF51_SPI1_PSELMISO,
-	/* TWI1 (I2C) */
-	&NRF51_TWI1_PSELSCL,
-	&NRF51_TWI1_PSELSDA,
-	/* SPIS1 (SPI SLAVE) */
-	&NRF51_SPIS1_PSELSCK,
-	&NRF51_SPIS1_PSELMISO,
-	&NRF51_SPIS1_PSELMOSI,
-	&NRF51_SPIS1_PSELCSN,
-	/* QDEC (ROTARY DECODER) */
-	&NRF51_QDEC_PSELLED,
-	&NRF51_QDEC_PSELA,
-	&NRF51_QDEC_PSELB,
-	/* LPCOMP (Low Power Comparator) */
-	&NRF51_LPCOMP_PSEL,
-};
-
-const unsigned int nrf51_alt_func_count = ARRAY_SIZE(nrf51_alt_funcs);
-
-/* Make sure the function table and defines stay in sync */
-BUILD_ASSERT(ARRAY_SIZE(nrf51_alt_funcs) == NRF51_MAX_ALT_FUNCS &&
-	NRF51_MAX_ALT_FUNCS <= GPIO_ALT_FUNC_MAX);
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	uint32_t val = 0;
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	if (flags & GPIO_OUTPUT)
-		val |= NRF51_PIN_CNF_DIR_OUTPUT;
-	else if (flags & GPIO_INPUT)
-		val |= NRF51_PIN_CNF_DIR_INPUT;
-
-	if (flags & GPIO_PULL_DOWN)
-		val |= NRF51_PIN_CNF_PULLDOWN;
-	else if (flags & GPIO_PULL_UP)
-		val |= NRF51_PIN_CNF_PULLUP;
-
-	/* TODO: Drive strength? H0D1? */
-	if (flags & GPIO_OPEN_DRAIN)
-		val |= NRF51_PIN_CNF_DRIVE_S0D1;
-
-	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_HIGH)
-			NRF51_GPIO0_OUTSET = mask;
-		else if (flags & GPIO_LOW)
-			NRF51_GPIO0_OUTCLR = mask;
-	}
-
-	/* Interrupt levels */
-	if (flags & GPIO_INT_SHARED) {
-		/*
-		 * There are no shared edge-triggered interrupts;
-		 * they're either high or low.
-		 */
-		ASSERT((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) == 0);
-		ASSERT((flags & GPIO_INT_LEVEL) != GPIO_INT_LEVEL);
-		if (flags & GPIO_INT_F_LOW)
-			val |= NRF51_PIN_CNF_SENSE_LOW;
-		else if (flags & GPIO_INT_F_HIGH)
-			val |= NRF51_PIN_CNF_SENSE_HIGH;
-	}
-
-	NRF51_PIN_CNF(bit) = val;
-}
-
-
-static void gpio_init(void)
-{
-	task_enable_irq(NRF51_PERID_GPIOTE);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	return !!(NRF51_GPIO0_IN & gpio_list[signal].mask);
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	if (value)
-		NRF51_GPIO0_OUTSET = gpio_list[signal].mask;
-	else
-		NRF51_GPIO0_OUTCLR = gpio_list[signal].mask;
-}
-
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-	int is_warm = 0;
-	int i;
-
-	if (NRF51_POWER_RESETREAS &
-			(NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */
-			 NRF51_POWER_RESETREAS_LPCOMP)) {
-		/* This is a warm reboot */
-		is_warm = 1;
-	}
-
-	/* Initialize Interrupt configuration */
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++)
-		gpio_ints[i] = NULL;
-	gpio_int_port = NULL;
-
-	/* Set all GPIOs to defaults */
-	for (i = 0; i < GPIO_COUNT; i++, g++) {
-		int flags = g->flags;
-
-		if (flags & GPIO_DEFAULT)
-			continue;
-
-		/*
-		 * If this is a warm reboot, don't set the output levels again.
-		 */
-		if (is_warm)
-			flags &= ~(GPIO_LOW | GPIO_HIGH);
-
-		/* Set up GPIO based on flags */
-		gpio_set_flags_by_mask(g->port, g->mask, flags);
-	}
-}
-
-/*
- * NRF51 doesn't have an alternate function table.
- * Use the pin select registers in place of the function number.
- */
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	uint32_t bit = GPIO_MASK_TO_NUM(mask);
-
-	ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */
-	ASSERT(port == GPIO_0);
-	ASSERT((func >= GPIO_ALT_FUNC_DEFAULT && func < nrf51_alt_func_count) ||
-		func == GPIO_ALT_FUNC_NONE);
-
-	/* Remove the previous setting(s) */
-	if (func == GPIO_ALT_FUNC_NONE) {
-		int i;
-		for (i = 0; i < nrf51_alt_func_count; i++) {
-			if (*(nrf51_alt_funcs[i]) == bit)
-				*(nrf51_alt_funcs[i]) = 0xffffffff;
-		}
-	} else {
-		*(nrf51_alt_funcs[func]) = bit;
-	}
-}
-
-
-/*
- *  Enable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- *
- */
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	int pin;
-	const struct gpio_info *g = gpio_list + signal;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		int int_num, free_slot = -1;
-		uint32_t event_config = 0;
-
-		for (int_num = 0; int_num < NRF51_GPIOTE_IN_COUNT; int_num++) {
-			if (gpio_ints[int_num] == g)
-				return EC_SUCCESS; /* This is already set up. */
-
-			if (gpio_ints[int_num] == NULL && free_slot == -1)
-				free_slot = int_num;
-		}
-
-		ASSERT(free_slot != -1);
-
-		gpio_ints[free_slot] = g;
-		pin = GPIO_MASK_TO_NUM(g->mask);
-		event_config = (pin << NRF51_GPIOTE_PSEL_POS) |
-			NRF51_GPIOTE_MODE_EVENT;
-
-		ASSERT(g->flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING));
-
-		/* RISING | FALLING = TOGGLE */
-		if (g->flags & GPIO_INT_F_RISING)
-			event_config |= NRF51_GPIOTE_POLARITY_LOTOHI;
-		if (g->flags & GPIO_INT_F_FALLING)
-			event_config |= NRF51_GPIOTE_POLARITY_HITOLO;
-
-		NRF51_GPIOTE_CONFIG(free_slot) = event_config;
-
-		/* Enable the IN[] interrupt. */
-		NRF51_GPIOTE_INTENSET = 1 << free_slot;
-
-	} else {
-		/* The first handler for the shared interrupt wins. */
-		if (gpio_int_port == NULL) {
-			gpio_int_port = g;
-
-			/* Enable the PORT interrupt. */
-			NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-		}
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- *  Disable the interrupt associated with the "signal"
- *  The architecture has one general (PORT)
- *  and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts.
- */
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	int i;
-
-	/* Fail if not implemented or no interrupt handler */
-	if (!g->mask || signal >= GPIO_IH_COUNT)
-		return EC_ERROR_INVAL;
-
-	/* If it's not shared, use INT0-INT3, otherwise use PORT. */
-	if (!(g->flags & GPIO_INT_SHARED)) {
-		for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-			/* Remove matching handler. */
-			if (gpio_ints[i] == g) {
-				/* Disable the interrupt */
-				NRF51_GPIOTE_INTENCLR =
-					1 << NRF51_GPIOTE_IN_BIT(i);
-				/* Zero the handler */
-				gpio_ints[i] = NULL;
-			}
-		}
-	} else {
-		/* Disable the interrupt */
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-		/* Zero the shared handler */
-		gpio_int_port = NULL;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Clear interrupt and run handler.
- */
-void gpio_interrupt(void)
-{
-	const struct gpio_info *g;
-	int i;
-	int signal;
-
-	for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) {
-		if (NRF51_GPIOTE_IN(i)) {
-			NRF51_GPIOTE_IN(i) = 0;
-			g = gpio_ints[i];
-			signal = g - gpio_list;
-			if (g && signal < GPIO_IH_COUNT)
-				gpio_irq_handlers[signal](signal);
-		}
-	}
-
-	if (NRF51_GPIOTE_PORT) {
-		NRF51_GPIOTE_PORT = 0;
-		g = gpio_int_port;
-		signal = g - gpio_list;
-		if (g && signal < GPIO_IH_COUNT)
-			gpio_irq_handlers[signal](signal);
-	}
-}
-DECLARE_IRQ(NRF51_PERID_GPIOTE, gpio_interrupt, 1);
diff --git a/chip/nrf51/hwtimer.c b/chip/nrf51/hwtimer.c
deleted file mode 100644
index 980a889657..0000000000
--- a/chip/nrf51/hwtimer.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Hardware timers driver.
- *
- * nRF51x has one fully functional hardware counter, but 4 stand-alone
- * capture/compare (CC) registers.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
-/*
- * capture/compare (CC) registers:
- *   CC_INTERRUPT -- used to interrupt next clock event.
- *   CC_CURRENT -- used to capture the current value.
- *   CC_OVERFLOW -- used to detect overflow on virtual timer (not hardware).
- */
-
-#define CC_INTERRUPT  0
-#define CC_CURRENT    1
-#define CC_OVERFLOW   2
-
-/* The nRF51 has 3 timers, use HWTIMER to specify which one is used here. */
-#define HWTIMER       0
-
-static uint32_t last_deadline;  /* cache of event set */
-
-/*
- * The nRF51x timer cannot be set to a specified value (reset to zero only).
- * Thus, we have to use a variable "shift" to maintain the offset between the
- * hardware value and virtual clock value.
- *
- * Once __hw_clock_source_set(ts) is called, the shift will be like:
- *
- *   virtual time  ------------------------------------------------
- *                  <----------> ^
- *                      shift    | ts
- *               0 |             |
- *   hardware      v
- *   counter time  ------------------------------------------------
- *
- *
- * Below diagram shows what it is when overflow happens.
- *
- *                       | now                                | prev_read
- *                       v                                    v
- *   virtual time  ------------------------------------------------
- *                 ---->                                    <------
- *                 shift                                      shift
- *                                                         |
- *   hardware                                              v
- *   counter time  ------------------------------------------------
- *
- */
-static uint32_t shift;
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	last_deadline = deadline;
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = deadline - shift;
-
-	/* enable interrupt */
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	return last_deadline;
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* disable interrupt */
-	NRF51_TIMER_INTENCLR(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT);
-}
-
-uint32_t __hw_clock_source_read(void)
-{
-	/* to capture the current value */
-	NRF51_TIMER_CAPTURE(HWTIMER, CC_CURRENT) = 1;
-	return NRF51_TIMER_CC(HWTIMER, CC_CURRENT) + shift;
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	shift = ts;
-
-	/* reset counter to zero */
-	NRF51_TIMER_STOP(HWTIMER) = 1;
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* So that no interrupt until next __hw_clock_event_set() */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = ts - 1;
-
-	/* Update the overflow point */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0 - shift;
-
-	/* Start the timer again */
-	NRF51_TIMER_START(HWTIMER) = 1;
-}
-
-
-/* Interrupt handler for timer */
-void timer_irq(void)
-{
-	int overflow = 0;
-
-	/* clear status */
-	NRF51_TIMER_COMPARE(HWTIMER, CC_INTERRUPT) = 0;
-
-	if (NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW)) {
-		NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW) = 0;
-		overflow = 1;
-	}
-
-	process_timers(overflow);
-}
-
-/* DECLARE_IRQ doesn't like the NRF51_PERID_TIMER(n) macro */
-BUILD_ASSERT(NRF51_PERID_TIMER(HWTIMER) == NRF51_PERID_TIMER0);
-DECLARE_IRQ(NRF51_PERID_TIMER0, timer_irq, 1);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-
-	/* Start the high freq crystal oscillator */
-	NRF51_CLOCK_HFCLKSTART = 1;
-	/* TODO: check if the crystal oscillator is running (HFCLKSTAT) */
-
-	/* 32-bit timer mode */
-	NRF51_TIMER_MODE(HWTIMER) = NRF51_TIMER_MODE_TIMER;
-	NRF51_TIMER_BITMODE(HWTIMER) = NRF51_TIMER_BITMODE_32;
-
-	/*
-	 * The external crystal oscillator is 16MHz (HFCLK).
-	 * Set the prescaler to 16 so that the timer counter is increasing
-	 * every micro-second (us).
-	 */
-	NRF51_TIMER_PRESCALER(HWTIMER) = 4;  /* actual value is 2**4 = 16 */
-
-	/* Not to trigger interrupt until __hw_clock_event_set() is called. */
-	NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = 0xffffffff;
-
-	/* Set to 0 so that the next overflow can trigger timer_irq(). */
-	NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0;
-	NRF51_TIMER_INTENSET(HWTIMER) =
-		1 << NRF51_TIMER_COMPARE_BIT(CC_OVERFLOW);
-
-	/* Clear the timer counter */
-	NRF51_TIMER_CLEAR(HWTIMER) = 1;
-
-	/* Override the count with the start value now that counting has
-	 * started. */
-	__hw_clock_source_set(start_t);
-
-	/* Enable interrupt */
-	task_enable_irq(NRF51_PERID_TIMER(HWTIMER));
-
-	/* Start the timer */
-	NRF51_TIMER_START(HWTIMER) = 1;
-
-	return NRF51_PERID_TIMER(HWTIMER);
-}
-
diff --git a/chip/nrf51/i2c.c b/chip/nrf51/i2c.c
deleted file mode 100644
index ff23152c89..0000000000
--- a/chip/nrf51/i2c.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ppi.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-#define I2C_TIMEOUT 20000
-
-/* Keep track of the PPI channel used for each port */
-static int i2c_ppi_chan[] = {-1, -1};
-
-static void i2c_init_port(unsigned int port);
-
-/* board-specific setup for post-I2C module init */
-void __board_i2c_post_init(int port)
-{
-}
-
-void board_i2c_post_init(int port)
-		__attribute__((weak, alias("__board_i2c_post_init")));
-
-static void i2c_init_port(unsigned int port)
-{
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	NRF51_TWI_PSELSCL(port) = NRF51_TWI_SCL_PIN(port);
-	NRF51_TWI_PSELSDA(port) = NRF51_TWI_SDA_PIN(port);
-	NRF51_TWI_FREQUENCY(port) = NRF51_TWI_FREQ(port);
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	NRF51_PPI_EEP(i2c_ppi_chan[port]) = (uint32_t)&NRF51_TWI_BB(port);
-	NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-		(uint32_t)&NRF51_TWI_SUSPEND(port);
-
-	/* Master enable */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_ENABLE_VAL;
-
-	if (!(i2c_raw_get_scl(port) && (i2c_raw_get_sda(port))))
-		CPRINTF("port %d could be wedged\n", port);
-}
-
-void i2c_init(void)
-{
-	int i, rv;
-
-	gpio_config_module(MODULE_I2C, 1);
-
-	for (i = 0; i < i2c_ports_used; i++) {
-		if (i2c_ppi_chan[i] == -1) {
-			rv = ppi_request_channel(&i2c_ppi_chan[i]);
-			ASSERT(rv == EC_SUCCESS);
-
-			i2c_init_port(i);
-		}
-	}
-}
-
-static void dump_i2c_reg(int port)
-{
-#ifdef CONFIG_I2C_DEBUG
-	CPRINTF("port      : %01d\n", port);
-	CPRINTF("Regs :\n");
-	CPRINTF(" 1: INTEN     : %08x\n", NRF51_TWI_INTEN(port));
-	CPRINTF(" 2: ERRORSRC  : %08x\n", NRF51_TWI_ERRORSRC(port));
-	CPRINTF(" 3: ENABLE    : %08x\n", NRF51_TWI_ENABLE(port));
-	CPRINTF(" 4: PSELSCL   : %08x\n", NRF51_TWI_PSELSCL(port));
-	CPRINTF(" 5: PSELSDA   : %08x\n", NRF51_TWI_PSELSDA(port));
-	CPRINTF(" 6: RXD       : %08x\n", NRF51_TWI_RXD(port));
-	CPRINTF(" 7: TXD       : %08x\n", NRF51_TWI_TXD(port));
-	CPRINTF(" 8: FREQUENCY : %08x\n", NRF51_TWI_FREQUENCY(port));
-	CPRINTF(" 9: ADDRESS   : %08x\n", NRF51_TWI_ADDRESS(port));
-	CPRINTF("Events :\n");
-	CPRINTF(" STOPPED   : %08x\n", NRF51_TWI_STOPPED(port));
-	CPRINTF(" RXDRDY    : %08x\n", NRF51_TWI_RXDRDY(port));
-	CPRINTF(" TXDSENT   : %08x\n", NRF51_TWI_TXDSENT(port));
-	CPRINTF(" ERROR     : %08x\n", NRF51_TWI_ERROR(port));
-	CPRINTF(" BB        : %08x\n", NRF51_TWI_BB(port));
-#endif /* CONFIG_I2C_DEBUG */
-}
-
-static void i2c_recover(int port)
-{
-	/*
-	 * Recovery of the TWI peripheral:
-	 * To recover a TWI peripheral that has been locked up you must use
-	 * the following code.
-	 * After the recover function it is important to reconfigure all
-	 * relevant TWI registers explicitly to ensure that it operates
-	 * correctly.
-	 *    TWI0:
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 0;
-	 *      nrf_delay_us(5);
-	 *      *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 1;
-	 *      NRF_TWI0->ENABLE =
-	 *         TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
-	 */
-	NRF51_TWI_ENABLE(port) = NRF51_TWI_DISABLE_VAL;
-	NRF51_TWI_POWER(port) = 0;
-	udelay(5);
-	NRF51_TWI_POWER(port) = 1;
-
-	i2c_init_port(port);
-}
-
-static void handle_i2c_error(int port, int rv)
-{
-	if (rv == EC_SUCCESS)
-		return;
-
-#ifdef CONFIG_I2C_DEBUG
-	if (rv != EC_ERROR_TIMEOUT)
-		CPRINTF("handle_i2c_error %d\n", rv);
-	else
-		CPRINTF("handle_i2c_error: Timeout\n");
-
-	dump_i2c_reg(port);
-#endif
-
-	/* This may be a little too heavy handed. */
-	i2c_recover(port);
-}
-
-static int i2c_master_write(const int port, const uint16_t slave_addr_flags,
-			    const uint8_t *data, int size, int stop)
-{
-	int bytes_sent;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_STRIP_FLAGS(slave_addr_flags);
-
-	/* Clear the sent bit */
-	NRF51_TWI_TXDSENT(port) = 0;
-
-	for (bytes_sent = 0; bytes_sent < size; bytes_sent++) {
-		/*Send a byte */
-		NRF51_TWI_TXD(port) = data[bytes_sent];
-
-		/* Only send a start for the first byte */
-		if (bytes_sent == 0)
-			NRF51_TWI_STARTTX(port) = 1;
-
-		/* Wait for ACK/NACK */
-		timeout = I2C_TIMEOUT;
-		while (timeout > 0 && NRF51_TWI_TXDSENT(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		/* Clear the sent bit */
-		NRF51_TWI_TXDSENT(port) = 0;
-	}
-
-	if (stop) {
-		NRF51_TWI_STOPPED(port) = 0;
-		NRF51_TWI_STOP(port) = 1;
-		timeout = 10;
-		while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-			timeout--;
-	}
-
-	return EC_SUCCESS;
-}
-
-static int i2c_master_read(const int port, const uint16_t slave_addr_flags,
-			   uint8_t *data, int size)
-{
-	int curr_byte;
-	int timeout = I2C_TIMEOUT;
-
-	NRF51_TWI_ADDRESS(port) = I2C_STRIP_FLAGS(slave_addr_flags);
-
-	if (size == 1) /* Last byte: stop after this one. */
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_STOP(port);
-	else
-		NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-			(uint32_t)&NRF51_TWI_SUSPEND(port);
-	NRF51_PPI_CHENSET = 1 << i2c_ppi_chan[port];
-
-	NRF51_TWI_RXDRDY(port) = 0;
-	NRF51_TWI_STARTRX(port) = 1;
-
-	for (curr_byte = 0; curr_byte < size; curr_byte++) {
-
-		/* Wait for data */
-		while (timeout > 0 && NRF51_TWI_RXDRDY(port) == 0 &&
-				NRF51_TWI_ERROR(port) == 0)
-			timeout--;
-
-		if (timeout == 0)
-			return EC_ERROR_TIMEOUT;
-
-		if (NRF51_TWI_ERROR(port))
-			return EC_ERROR_UNKNOWN;
-
-		data[curr_byte] = NRF51_TWI_RXD(port);
-		NRF51_TWI_RXDRDY(port) = 0;
-
-		/* Second to the last byte: stop next time. */
-		if (curr_byte == size-2)
-			NRF51_PPI_TEP(i2c_ppi_chan[port]) =
-				(uint32_t)&NRF51_TWI_STOP(port);
-
-		/*
-		 * According to nRF51822-PAN v2.4 (Product Anomaly Notice),
-		 * the I2C locks up when RESUME is triggered too soon.
-		 * "the firmware should ensure that the time between receiving
-		 * the RXDRDY event and trigging the RESUME task is at least
-		 * two times the TWI clock period (i.e. 20 μs at 100 kbps).
-		 * Provided the TWI slave doesn’t do clock stretching during
-		 * the ACK bit, this will be enough to avoid the RESUME task
-		 * hit the end of the ACK bit. If this fails, a recovery of
-		 * the peripheral will be necessary, see i2c_recover.
-		 */
-		udelay(20);
-		NRF51_TWI_RESUME(port) = 1;
-	}
-
-	timeout = I2C_TIMEOUT;
-	while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0)
-		timeout--;
-
-	NRF51_TWI_STOP(port) = 0;
-
-	NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port];
-
-	return EC_SUCCESS;
-}
-
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
-{
-	int rv = EC_SUCCESS;
-
-	ASSERT(out || !out_bytes);
-	ASSERT(in || !in_bytes);
-
-	if (out_bytes)
-		rv = i2c_master_write(port, slave_addr_flags,
-				      out, out_bytes,
-				      in_bytes ? 0 : 1);
-	if (rv == EC_SUCCESS && in_bytes)
-		rv = i2c_master_read(port, slave_addr_flags,
-				     in, in_bytes);
-
-	handle_i2c_error(port, rv);
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal g;
-
-	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal g;
-
-	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
-		return gpio_get_level(g);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-}
-
diff --git a/chip/nrf51/keyboard_raw.c b/chip/nrf51/keyboard_raw.c
deleted file mode 100644
index 779c68454c..0000000000
--- a/chip/nrf51/keyboard_raw.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Raw keyboard I/O layer for nRF51
- *
- * To make this code portable, we rely heavily on looping over the keyboard
- * input and output entries in the board's gpio_list[]. Each set of inputs or
- * outputs must be listed in consecutive, increasing order so that scan loops
- * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are
- * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX).
- */
-
-#include "gpio.h"
-#include "keyboard_config.h"
-#include "keyboard_raw.h"
-#include "keyboard_scan.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-
-/* Mask of output pins for driving. */
-static unsigned int col_mask;
-
-void keyboard_raw_init(void)
-{
-	int i;
-
-	/* Initialize col_mask */
-	col_mask = 0;
-	for (i = 0; i < keyboard_cols; i++)
-		col_mask |= gpio_list[GPIO_KB_OUT00 + i].mask;
-
-	/* Ensure interrupts are disabled */
-	keyboard_raw_enable_interrupt(0);
-}
-
-void keyboard_raw_task_start(void)
-{
-	/*
-	 * Enable the interrupt for keyboard matrix inputs.
-	 * One is enough, since they are shared.
-	 */
-	gpio_enable_interrupt(GPIO_KB_IN00);
-}
-
-test_mockable void keyboard_raw_drive_column(int out)
-{
-	/* tri-state all first */
-	NRF51_GPIO0_OUTSET = col_mask;
-
-	/* drive low for specified pin(s) */
-	if (out == KEYBOARD_COLUMN_ALL)
-		NRF51_GPIO0_OUTCLR = col_mask;
-	else if (out != KEYBOARD_COLUMN_NONE)
-		NRF51_GPIO0_OUTCLR = gpio_list[GPIO_KB_OUT00 + out].mask;
-}
-
-test_mockable int keyboard_raw_read_rows(void)
-{
-	int i;
-	int state = 0;
-
-	for (i = 0; i < KEYBOARD_ROWS; i++) {
-		if (NRF51_GPIO0_IN & gpio_list[GPIO_KB_IN00 + i].mask)
-			state |= 1 << i;
-	}
-
-	/* Invert it so 0=not pressed, 1=pressed */
-	return state ^ 0xff;
-}
-
-void keyboard_raw_enable_interrupt(int enable)
-{
-	if (enable) {
-		/*
-		 * Clear the PORT event before enabling the interrupt.
-		 */
-		NRF51_GPIOTE_PORT = 0;
-		NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT;
-	} else {
-		NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT;
-	}
-}
-
-void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_KEYSCAN);
-}
diff --git a/chip/nrf51/ppi.c b/chip/nrf51/ppi.c
deleted file mode 100644
index 016cbf3008..0000000000
--- a/chip/nrf51/ppi.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ppi.h"
-#include "registers.h"
-#include "util.h"
-
-#define NRF51_PPI_FIRST_PP_CH NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_LAST_PP_CH  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-static uint32_t channels_in_use;
-static uint32_t channel_groups_in_use;
-
-int ppi_request_pre_programmed_channel(int ppi_chan)
-{
-	ASSERT(ppi_chan >= NRF51_PPI_FIRST_PP_CH &&
-		ppi_chan <= NRF51_PPI_LAST_PP_CH);
-
-	if (channels_in_use & BIT(ppi_chan))
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(ppi_chan);
-
-	return EC_SUCCESS;
-}
-
-int ppi_request_channel(int *ppi_chan)
-{
-	int chan;
-
-	for (chan = 0; chan < NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS; chan++)
-		if ((channels_in_use & BIT(chan)) == 0)
-			break;
-
-	if (chan == NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS)
-		return EC_ERROR_BUSY;
-
-	channels_in_use |= BIT(chan);
-	*ppi_chan = chan;
-	return EC_SUCCESS;
-}
-
-void ppi_release_channel(int ppi_chan)
-{
-	channels_in_use &= ~BIT(ppi_chan);
-}
-
-void ppi_release_group(int ppi_group)
-{
-	channel_groups_in_use &= ~BIT(ppi_group);
-}
-
-int ppi_request_group(int *ppi_group)
-{
-	int group;
-
-	for (group = 0; group < NRF51_PPI_NUM_GROUPS; group++)
-		if ((channel_groups_in_use & BIT(group)) == 0)
-			break;
-
-	if (group == NRF51_PPI_NUM_GROUPS)
-		return EC_ERROR_BUSY;
-
-	channel_groups_in_use |= BIT(group);
-	*ppi_group = group;
-	return EC_SUCCESS;
-}
diff --git a/chip/nrf51/ppi.h b/chip/nrf51/ppi.h
deleted file mode 100644
index bbb74a2cf0..0000000000
--- a/chip/nrf51/ppi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * PPI channels are a way to connect NRF51 EVENTs to TASKs without software
- * involvement. They are like SHORTs, except between peripherals.
- *
- * PPI groups are user-defined sets of channels that can be enabled and disabled
- * together.
- */
-
-/*
- * Reserve a pre-programmed PPI channel.
- *
- * Return EC_SUCCESS if ppi_chan is a pre-programmed channel that was not in
- * use, otherwise returns EC_ERROR_BUSY.
- */
-int ppi_request_pre_programmed_channel(int ppi_chan);
-
-/*
- * Reserve an available PPI channel.
- *
- * Return EC_SUCCESS and set the value of ppi_chan to an available PPI
- * channel.  If no channel is available, return EC_ERROR_BUSY.
- */
-int ppi_request_channel(int *ppi_chan);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_channel(int ppi_chan);
-
-/*
- * Reserve a PPI group.
- *
- * Return EC_SUCCESS and set the value of ppi_group to an available PPI
- * group.  If no group is available, return EC_ERROR_BUSY.
- */
-int ppi_request_group(int *ppi_group);
-
-/* Release a PPI channel which was reserved with ppi_request_*_channel.  */
-void ppi_release_group(int ppi_group);
diff --git a/chip/nrf51/radio.c b/chip/nrf51/radio.c
deleted file mode 100644
index af9d029a0d..0000000000
--- a/chip/nrf51/radio.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "radio.h"
-
-int radio_disable(void)
-{
-	int timeout = 10000;
-
-	NRF51_RADIO_DISABLED = 0;
-	NRF51_RADIO_DISABLE = 1;
-
-	while (!NRF51_RADIO_DISABLED && timeout > 0)
-		timeout--;
-
-	if (timeout == 0)
-		return EC_ERROR_TIMEOUT;
-
-	return EC_SUCCESS;
-}
-
-int radio_init(enum nrf51_radio_mode_t mode)
-{
-	int err_code = radio_disable();
-
-	if (mode == BLE_1MBIT) {
-		NRF51_RADIO_MODE = NRF51_RADIO_MODE_BLE_1MBIT;
-
-		NRF51_RADIO_TIFS = 150;	/* Bluetooth 4.1 Vol 6 pg 58 4.1 */
-
-		/*
-		 * BLE never sends or receives two packets in a row.
-		 * Enabling the radio means we want to transmit or receive.
-		 * After transmission, disable as quickly as possible.
-		 */
-		NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START |
-				NRF51_RADIO_SHORTS_END_DISABLE;
-
-		/* Use factory parameters if available */
-		if (!(NRF51_FICR_OVERRIDEEN & NRF51_FICR_OVERRIDEEN_BLE_BIT_N)
-		    ) {
-			int i;
-
-			for (i = 0; i < 4; i++) {
-				NRF51_RADIO_OVERRIDE(i) =
-					NRF51_FICR_BLE_1MBIT(i);
-			}
-			NRF51_RADIO_OVERRIDE(4) = NRF51_FICR_BLE_1MBIT(4) |
-				NRF51_RADIO_OVERRIDE_EN;
-		}
-	} else {
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	return err_code;
-}
-
diff --git a/chip/nrf51/radio.h b/chip/nrf51/radio.h
deleted file mode 100644
index 5b7e764fb9..0000000000
--- a/chip/nrf51/radio.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Radio interface for Chrome EC */
-
-#ifndef __NRF51_RADIO_H
-#define __NRF51_RADIO_H
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "registers.h"
-
-#ifndef NRF51_RADIO_MAX_PAYLOAD
-	#define NRF51_RADIO_MAX_PAYLOAD 253
-#endif
-
-#define RADIO_DONE (NRF51_RADIO_END == 1)
-
-enum nrf51_radio_mode_t {
-	BLE_1MBIT = NRF51_RADIO_MODE_BLE_1MBIT,
-};
-
-struct nrf51_radio_packet_t {
-	uint8_t s0; /* First byte */
-	uint8_t length; /* Length field */
-	uint8_t s1; /* Bits after length */
-	uint8_t payload[NRF51_RADIO_MAX_PAYLOAD];
-} __packed;
-
-int radio_init(enum nrf51_radio_mode_t mode);
-
-int radio_disable(void);
-
-#endif  /* __NRF51_RADIO_H */
diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c
deleted file mode 100644
index 6c20874f4e..0000000000
--- a/chip/nrf51/radio_test.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "bluetooth_le.h" /* chan2freq */
-#include "btle_hci_int.h"
-#include "console.h"
-#include "radio.h"
-#include "radio_test.h"
-#include "registers.h"
-#include "timer.h"
-#include "util.h"
-
-#define BLE_TEST_TYPE_PRBS9   0
-#define BLE_TEST_TYPE_F0      1
-#define BLE_TEST_TYPE_AA      2
-#define BLE_TEST_TYPE_PRBS15  3
-#define BLE_TEST_TYPE_FF      4
-#define BLE_TEST_TYPE_00      5
-#define BLE_TEST_TYPE_0F      6
-#define BLE_TEST_TYPE_55      7
-
-#define BLE_TEST_TYPES_IMPLEMENTED 0xf6 /* No PRBS yet */
-
-static struct nrf51_ble_packet_t rx_packet;
-static struct nrf51_ble_packet_t tx_packet;
-static uint32_t rx_end;
-
-static int test_in_progress;
-
-void ble_test_stop(void)
-{
-	test_in_progress = 0;
-}
-
-static uint32_t prbs_lfsr;
-static uint32_t prbs_poly;
-
-/*
- * This is a Galois LFSR, the polynomial is the counterpart of the Fibonacci
- * LFSR in the doc.  It requires fewer XORs to implement in software.
- * This also means that the initial value is different.
- */
-static uint8_t prbs_next_byte(void)
-{
-	int i;
-	int lsb;
-	uint8_t rv = 0;
-
-	for (i = 0; i < 8; i++) {
-		lsb = prbs_lfsr & 1;
-		rv |= lsb << i;
-		prbs_lfsr = prbs_lfsr >> 1;
-		if (lsb)
-			prbs_lfsr ^= prbs_poly;
-	}
-	return rv;
-}
-
-void ble_test_fill_tx_packet(int type, int len)
-{
-	int i;
-
-	tx_packet.s0 = type & 0xf;
-	tx_packet.length = len;
-
-	switch (type) {
-	case BLE_TEST_TYPE_PRBS9:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x108;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_PRBS15:
-		prbs_lfsr = 0xf;
-		prbs_poly = 0x6000;
-		for (i = 0; i < len; i++)
-			tx_packet.payload[i] = prbs_next_byte();
-		break;
-	case BLE_TEST_TYPE_F0:
-		memset(tx_packet.payload, 0xF0, len);
-		break;
-	case BLE_TEST_TYPE_AA:
-		memset(tx_packet.payload, 0xAA, len);
-		break;
-	case BLE_TEST_TYPE_FF:
-		memset(tx_packet.payload, 0xFF, len);
-		break;
-	case BLE_TEST_TYPE_00:
-		memset(tx_packet.payload, 0x00, len);
-		break;
-	case BLE_TEST_TYPE_0F:
-		memset(tx_packet.payload, 0x0F, len);
-		break;
-	case BLE_TEST_TYPE_55:
-		memset(tx_packet.payload, 0x55, len);
-		break;
-	default:
-		break;
-	}
-}
-
-static int ble_test_init(int chan)
-{
-	int rv = radio_init(BLE_1MBIT);
-
-	if (rv)
-		return HCI_ERR_Hardware_Failure;
-
-	if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL)
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */
-	/* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */
-	/* 0x1_0000_0000_0000_0110_0101_1011 */
-	NRF51_RADIO_CRCPOLY = 0x100065B;
-	NRF51_RADIO_CRCINIT = 0x555555;
-
-	NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM;
-
-	/* The testing address is the inverse of the advertising address. */
-	NRF51_RADIO_BASE0 = (~BLE_ADV_ACCESS_ADDRESS) << 8;
-
-	NRF51_RADIO_PREFIX0 = (~BLE_ADV_ACCESS_ADDRESS) >> 24;
-
-	NRF51_RADIO_TXADDRESS = 0;
-	NRF51_RADIO_RXADDRESSES = 1;
-
-	NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_TEST;
-
-	NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_TEST;
-
-	NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(2*chan + 2402);
-
-	test_in_progress = 1;
-	return rv;
-}
-
-int ble_test_rx_init(int chan)
-{
-	NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet;
-	return ble_test_init(chan);
-}
-
-int ble_test_tx_init(int chan, int len, int type)
-{
-	if ((BIT(type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 ||
-			(len < 0 || len > BLE_MAX_TEST_PAYLOAD_OCTETS))
-		return HCI_ERR_Invalid_HCI_Command_Parameters;
-
-	ble_test_fill_tx_packet(type, len);
-	NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet;
-
-	return ble_test_init(chan);
-}
-
-void ble_test_tx(void)
-{
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_TXEN = 1;
-}
-
-int ble_test_rx(void)
-{
-	int retries = 100;
-
-	NRF51_RADIO_END = 0;
-	NRF51_RADIO_RXEN = 1;
-
-	do {
-		retries--;
-		if (retries <= 0) {
-			radio_disable();
-			return EC_ERROR_TIMEOUT;
-		}
-		usleep(100);
-	} while (!NRF51_RADIO_END);
-
-	rx_end = get_time().le.lo;
-
-	return EC_SUCCESS;
-}
-
diff --git a/chip/nrf51/radio_test.h b/chip/nrf51/radio_test.h
deleted file mode 100644
index 591b78a78c..0000000000
--- a/chip/nrf51/radio_test.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Radio test interface for NRF51
- *
- * These functions implement parts of the Direct Test Mode functionality in
- * the Bluetooth Spec.
- */
-
-#ifndef __NRF51_RADIO_TEST_H
-#define __NRF51_RADIO_TEST_H
-
-#define BLE_MAX_TEST_PAYLOAD_OCTETS       37
-#define BLE_MAX_TEST_CHANNEL              39
-#define BLE_MIN_TEST_CHANNEL              0
-
-#define NRF51_RADIO_PCNF0_TEST NRF51_RADIO_PCNF0_ADV_DATA
-
-#define BLE_TEST_WHITEN           0
-
-#define NRF51_RADIO_PCNF1_TEST \
-	NRF51_RADIO_PCNF1_VAL(BLE_MAX_TEST_PAYLOAD_OCTETS, \
-			      EXTRA_RECEIVE_BYTES, \
-			      BLE_ACCESS_ADDRESS_BYTES - 1, \
-			      BLE_TEST_WHITEN)
-
-/*
- * Prepare the radio for transmitting packets.  The value of chan must be
- * between 0 and 39 inclusive.  The maximum length is 37.
- */
-
-int ble_test_tx_init(int chan, int type, int len);
-int ble_test_rx_init(int chan);
-void ble_test_tx(void);
-int ble_test_rx(void);
-void ble_test_stop(void);
-
-#endif /* __NRF51_RADIO_TEST_H */
diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h
deleted file mode 100644
index daf014df72..0000000000
--- a/chip/nrf51/registers.h
+++ /dev/null
@@ -1,720 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Register map for STM32 processor
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-
-/*
- *  Peripheral IDs
- *
- *  nRF51 has very good design that the peripheral IDs is actually the IRQ#.
- *  Thus, the following numbers are used in DECLARE_IRQ(), task_enable_irq()
- *  and task_disable_irq().
- */
-#define NRF51_PERID_POWER   0
-#define NRF51_PERID_CLOCK   0
-#define NRF51_PERID_RADIO   1
-#define NRF51_PERID_USART   2
-#define NRF51_PERID_SPI0    3
-#define NRF51_PERID_TWI0    3
-#define NRF51_PERID_SPI1    4
-#define NRF51_PERID_TWI1    4
-#define NRF51_PERID_SPIS    4
-#define NRF51_PERID_GPIOTE  6
-#define NRF51_PERID_ADC     7
-#define NRF51_PERID_TIMER0  8
-#define NRF51_PERID_TIMER1  9
-#define NRF51_PERID_TIMER2  10
-#define NRF51_PERID_RTC     11
-#define NRF51_PERID_TEMP    12
-#define NRF51_PERID_RNG     13
-#define NRF51_PERID_ECB     14
-#define NRF51_PERID_CCM     15
-#define NRF51_PERID_AAR     16
-#define NRF51_PERID_WDT     17
-#define NRF51_PERID_QDEC    18
-#define NRF51_PERID_LPCOMP  19
-#define NRF51_PERID_NVMC    30
-#define NRF51_PERID_PPI     31
-
-/*
- * The nRF51 allows any pin to be mapped to any function.  This
- * doesn't fit well with the notion of the alternate function table.
- * Implement an alternate function table.  See ./gpio.c.
- */
-
-	/* UART */
-#define NRF51_UART_ALT_FUNC_RTS        0
-#define NRF51_UART_ALT_FUNC_TXD        1
-#define NRF51_UART_ALT_FUNC_CTS        2
-#define NRF51_UART_ALT_FUNC_RXD        3
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI0_ALT_FUNC_SCK        4
-#define NRF51_SPI0_ALT_FUNC_MOSI       5
-#define NRF51_SPI0_ALT_FUNC_MISO       6
-	/* TWI0 (I2C) */
-#define NRF51_TWI0_ALT_FUNC_SCL        7
-#define NRF51_TWI0_ALT_FUNC_SDA        8
-	/* SPI1 (SPI Master) */
-#define NRF51_SPI1_ALT_FUNC_SCK        9
-#define NRF51_SPI1_ALT_FUNC_MOSI       10
-#define NRF51_SPI1_ALT_FUNC_MISO       11
-	/* TWI1 (I2C) */
-#define NRF51_TWI1_ALT_FUNC_SCL        12
-#define NRF51_TWI1_ALT_FUNC_SDA        13
-	/* SPIS1 (SPI SLAVE) */
-#define NRF51_SPIS1_ALT_FUNC_SCK       14
-#define NRF51_SPIS1_ALT_FUNC_MISO      15
-#define NRF51_SPIS1_ALT_FUNC_MOSI      16
-#define NRF51_SPIS1_ALT_FUNC_CSN       17
-	/* QDEC (ROTARY DECODER) */
-#define NRF51_QDEC_ALT_FUNC_LED        18
-#define NRF51_QDEC_ALT_FUNC_A          19
-#define NRF51_QDEC_ALT_FUNC_B          20
-	/* LPCOMP (Low Power Comparator) */
-#define NRF51_LPCOMP_ALT_FUNC          21
-#define NRF51_MAX_ALT_FUNCS            22
-
-/*
- * Configuration Registers
- */
-
-/*
- * FICR
- */
-#define NRF51_FICR_BASE                0x10000000
-#define NRF51_FICR_CODEPAGESIZE        REG32(NRF51_FICR_BASE + 0x010)
-#define NRF51_FICR_CLENR0              REG32(NRF51_FICR_BASE + 0x014)
-#define NRF51_FICR_PPFC                REG32(NRF51_FICR_BASE + 0x028)
-#define NRF51_FICR_NUMRAMBLOCK         REG32(NRF51_FICR_BASE + 0x02C)
-#define NRF51_FICR_SIZERAMBLOCK(n)     REG32(NRF51_FICR_BASE + 0x034 + ((n)*4))
-#define NRF51_FICR_CONFIGID            REG32(NRF51_FICR_BASE + 0x05C)
-#define NRF51_FICR_DEVICEID(n)         REG32(NRF51_FICR_BASE + 0x060 + ((n)*4))
-#define NRF51_FICR_ER(n)               REG32(NRF51_FICR_BASE + 0x080 + ((n)*4))
-#define NRF51_FICR_IR(n)               REG32(NRF51_FICR_BASE + 0x090 + ((n)*4))
-#define NRF51_FICR_DEVICEADDRTYPE      REG32(NRF51_FICR_BASE + 0x0A0)
-#define NRF51_FICR_DEVICEADDR(n)       REG32(NRF51_FICR_BASE + 0x0A4 + ((n)*4))
-#define NRF51_FICR_OVERRIDEEN          REG32(NRF51_FICR_BASE + 0x0AC)
-#define NRF51_FICR_BLE_1MBIT(n)        REG32(NRF51_FICR_BASE + 0x0EC + ((n)*4))
-
-/* DEVICEADDRTYPE */
-#define NRF51_FICR_DEVICEADDRTYPE_RANDOM      1
-
-/* OVERRIDEEN */
-#define NRF51_FICR_OVERRIDEEN_NRF_BIT_N       1
-#define NRF51_FICR_OVERRIDEEN_BLE_BIT_N       8
-
-/*
- * UICR
- */
-#define NRF51_UICR_BASE                0x10001000
-#define NRF51_UICR_CLENR0              REG32(NRF51_UICR_BASE + 0x000)
-#define NRF51_UICR_RBPCONF             REG32(NRF51_UICR_BASE + 0x004)
-#define NRF51_UICR_XTALFREQ            REG32(NRF51_UICR_BASE + 0x008)
-#define NRF51_UICR_FWID                REG32(NRF51_UICR_BASE + 0x010)
-#define NRF51_UICR_FWID_CUSTOMER(n)    REG32(NRF51_UICR_BASE + 0x080 + ((n)*4))
-
-#define NRF51_UICR_XTALFREQ_16MHZ      0xFF
-#define NRF51_UICR_XTALFREQ_32MHZ      0x00
-
-/*
- * Devices
- */
-
-/*
- *  Power
- */
-#define NRF51_POWER_BASE    0x40000000
-/* Tasks */
-#define NRF51_POWER_CONSTLAT  REG32(NRF51_POWER_BASE + 0x078)
-#define NRF51_POWER_LOWPWR    REG32(NRF51_POWER_BASE + 0x07C)
-/* Events */
-#define NRF51_POWER_POFWARN   REG32(NRF51_POWER_BASE + 0x108)
-/* Registers */
-#define NRF51_POWER_INTENSET  REG32(NRF51_POWER_BASE + 0x304)
-#define NRF51_POWER_INTENCLR  REG32(NRF51_POWER_BASE + 0x308)
-#define NRF51_POWER_RESETREAS REG32(NRF51_POWER_BASE + 0x400)
-#define NRF51_POWER_SYSTEMOFF REG32(NRF51_POWER_BASE + 0x500)
-#define NRF51_POWER_POFCON    REG32(NRF51_POWER_BASE + 0x510)
-#define NRF51_POWER_GPREGRET  REG32(NRF51_POWER_BASE + 0x51C)
-#define NRF51_POWER_RAMON     REG32(NRF51_POWER_BASE + 0x524)
-#define NRF51_POWER_RESET     REG32(NRF51_POWER_BASE + 0x544)
-#define NRF51_POWER_DCDCEN    REG32(NRF51_POWER_BASE + 0x578)
-
-#define NRF51_POWER_RESETREAS_RESETPIN          0x00001
-#define NRF51_POWER_RESETREAS_DOG               0x00002
-#define NRF51_POWER_RESETREAS_SREQ              0x00004
-#define NRF51_POWER_RESETREAS_LOCKUP            0x00008
-#define NRF51_POWER_RESETREAS_OFF               0x10000
-#define NRF51_POWER_RESETREAS_LPCOMP            0x20000
-#define NRF51_POWER_RESETREAS_DIF               0x40000
-
-
-/*
- *  Clock
- */
-#define NRF51_CLOCK_BASE    0x40000000
-/* Tasks */
-#define NRF51_CLOCK_HFCLKSTART REG32(NRF51_CLOCK_BASE + 0x000)
-#define NRF51_CLOCK_HFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x004)
-#define NRF51_CLOCK_LFCLKSTART REG32(NRF51_CLOCK_BASE + 0x008)
-#define NRF51_CLOCK_LFCLKSTOP  REG32(NRF51_CLOCK_BASE + 0x00C)
-#define NRF51_CLOCK_CAL     REG32(NRF51_CLOCK_BASE + 0x010)
-#define NRF51_CLOCK_CTSTART REG32(NRF51_CLOCK_BASE + 0x014)
-#define NRF51_CLOCK_CTSTOP  REG32(NRF51_CLOCK_BASE + 0x018)
-/* Events */
-#define NRF51_CLOCK_HFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x100)
-#define NRF51_CLOCK_LFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x104)
-#define NRF51_CLOCK_DONE    REG32(NRF51_CLOCK_BASE + 0x10C)
-#define NRF51_CLOCK_CCTO    REG32(NRF51_CLOCK_BASE + 0x110)
-/* Registers */
-#define NRF51_CLOCK_INTENSET  REG32(NRF51_CLOCK_BASE + 0x304)
-#define NRF51_CLOCK_INTENCLR  REG32(NRF51_CLOCK_BASE + 0x308)
-#define NRF51_CLOCK_HFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x40C)
-#define NRF51_CLOCK_LFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x418)
-#define NRF51_CLOCK_LFCLKSRC  REG32(NRF51_CLOCK_BASE + 0x518)
-#define NRF51_CLOCK_CTIV      REG32(NRF51_CLOCK_BASE + 0x538)
-#define NRF51_CLOCK_XTALFREQ  REG32(NRF51_CLOCK_BASE + 0x550)
-
-/*
- *  Radio
- */
-#define NRF51_RADIO_BASE    0x40001000
-/* Tasks */
-#define NRF51_RADIO_TXEN      REG32(NRF51_RADIO_BASE + 0x000)
-#define NRF51_RADIO_RXEN      REG32(NRF51_RADIO_BASE + 0x004)
-#define NRF51_RADIO_START     REG32(NRF51_RADIO_BASE + 0x008)
-#define NRF51_RADIO_STOP      REG32(NRF51_RADIO_BASE + 0x00C)
-#define NRF51_RADIO_DISABLE   REG32(NRF51_RADIO_BASE + 0x010)
-#define NRF51_RADIO_RSSISTART REG32(NRF51_RADIO_BASE + 0x014)
-#define NRF51_RADIO_RSSISTOP  REG32(NRF51_RADIO_BASE + 0x018)
-#define NRF51_RADIO_BCSTART   REG32(NRF51_RADIO_BASE + 0x01C)
-#define NRF51_RADIO_BCSTOP    REG32(NRF51_RADIO_BASE + 0x020)
-/* Events */
-#define NRF51_RADIO_READY     REG32(NRF51_RADIO_BASE + 0x100)
-#define NRF51_RADIO_ADDRESS   REG32(NRF51_RADIO_BASE + 0x104)
-#define NRF51_RADIO_PAYLOAD   REG32(NRF51_RADIO_BASE + 0x108)
-#define NRF51_RADIO_END       REG32(NRF51_RADIO_BASE + 0x10C)
-#define NRF51_RADIO_DISABLED  REG32(NRF51_RADIO_BASE + 0x110)
-#define NRF51_RADIO_DEVMATCH  REG32(NRF51_RADIO_BASE + 0x114)
-#define NRF51_RADIO_DEVMISS   REG32(NRF51_RADIO_BASE + 0x118)
-#define NRF51_RADIO_RSSIEND   REG32(NRF51_RADIO_BASE + 0x11C)
-#define NRF51_RADIO_BCMATCH   REG32(NRF51_RADIO_BASE + 0x128)
-/* Registers */
-#define NRF51_RADIO_SHORTS      REG32(NRF51_RADIO_BASE + 0x200)
-#define NRF51_RADIO_INTENSET    REG32(NRF51_RADIO_BASE + 0x304)
-#define NRF51_RADIO_INTENCLR    REG32(NRF51_RADIO_BASE + 0x308)
-#define NRF51_RADIO_CRCSTATUS   REG32(NRF51_RADIO_BASE + 0x400)
-#define NRF51_RADIO_RXMATCH     REG32(NRF51_RADIO_BASE + 0x408)
-#define NRF51_RADIO_RXCRC       REG32(NRF51_RADIO_BASE + 0x40C)
-#define NRF51_RADIO_DAI         REG32(NRF51_RADIO_BASE + 0x410)
-#define NRF51_RADIO_PACKETPTR   REG32(NRF51_RADIO_BASE + 0x504)
-#define NRF51_RADIO_FREQUENCY   REG32(NRF51_RADIO_BASE + 0x508)
-#define NRF51_RADIO_TXPOWER     REG32(NRF51_RADIO_BASE + 0x50C)
-#define NRF51_RADIO_MODE        REG32(NRF51_RADIO_BASE + 0x510)
-#define NRF51_RADIO_PCNF0       REG32(NRF51_RADIO_BASE + 0x514)
-#define NRF51_RADIO_PCNF1       REG32(NRF51_RADIO_BASE + 0x518)
-#define NRF51_RADIO_BASE0       REG32(NRF51_RADIO_BASE + 0x51C)
-#define NRF51_RADIO_BASE1       REG32(NRF51_RADIO_BASE + 0x520)
-#define NRF51_RADIO_PREFIX0     REG32(NRF51_RADIO_BASE + 0x524)
-#define NRF51_RADIO_PREFIX1     REG32(NRF51_RADIO_BASE + 0x528)
-#define NRF51_RADIO_TXADDRESS   REG32(NRF51_RADIO_BASE + 0x52C)
-#define NRF51_RADIO_RXADDRESSES REG32(NRF51_RADIO_BASE + 0x530)
-#define NRF51_RADIO_CRCCNF      REG32(NRF51_RADIO_BASE + 0x534)
-#define NRF51_RADIO_CRCPOLY     REG32(NRF51_RADIO_BASE + 0x538)
-#define NRF51_RADIO_CRCINIT     REG32(NRF51_RADIO_BASE + 0x53C)
-#define NRF51_RADIO_TEST        REG32(NRF51_RADIO_BASE + 0x540)
-#define NRF51_RADIO_TIFS        REG32(NRF51_RADIO_BASE + 0x544)
-#define NRF51_RADIO_RSSISAMPLE  REG32(NRF51_RADIO_BASE + 0x548)
-/* NRF51_RADIO_STATE (0x550) is Broken (PAN 2.4) */
-#define NRF51_RADIO_DATAWHITEIV REG32(NRF51_RADIO_BASE + 0x554)
-#define NRF51_RADIO_BCC         REG32(NRF51_RADIO_BASE + 0x560)
-#define NRF51_RADIO_DAB(n)      REG32(NRF51_RADIO_BASE + 0x600 + ((n) * 4))
-#define NRF51_RADIO_DAP(n)      REG32(NRF51_RADIO_BASE + 0x620 + ((n) * 4))
-#define NRF51_RADIO_DACNF       REG32(NRF51_RADIO_BASE + 0x640)
-#define NRF51_RADIO_OVERRIDE(n) REG32(NRF51_RADIO_BASE + 0x724 + ((n) * 4))
-#define NRF51_RADIO_POWER       REG32(NRF51_RADIO_BASE + 0xFFC)
-
-/* Shorts */
-#define NRF51_RADIO_SHORTS_READY_START                0x001
-#define NRF51_RADIO_SHORTS_END_DISABLE                0x002
-#define NRF51_RADIO_SHORTS_DISABLED_TXEN              0x004
-#define NRF51_RADIO_SHORTS_DISABLED_RXEN              0x008
-#define NRF51_RADIO_SHORTS_ADDRESS_RSSISTART          0x010
-/* NRF51_RADIO_SHORTS_END_START (0x20) is Broken (PAN 2.4) */
-#define NRF51_RADIO_SHORTS_ADDRESS_BCSTART            0x040
-#define NRF51_RADIO_SHORTS_DISABLED_RSSISTOP          0x100
-
-/* For RADIO.INTEN bits */
-#define NRF51_RADIO_READY_BIT                         0
-#define NRF51_RADIO_ADDRESS_BIT                       1
-#define NRF51_RADIO_PAYLOAD_BIT                       2
-#define NRF51_RADIO_END_BIT                           3
-#define NRF51_RADIO_DISABLED_BIT                      4
-#define NRF51_RADIO_DEVMATCH_BIT                      5
-#define NRF51_RADIO_DEVMISS_BIT                       6
-#define NRF51_RADIO_RSSIEND_BIT                       7
-#define NRF51_RADIO_BCMATCH_BIT                       10
-
-/* CRC Status */
-#define NRF51_RADIO_CRCSTATUS_OK                      0x1
-
-/* Frequency (in MHz) */
-#define NRF51_RADIO_FREQUENCY_VAL(x)                  ((x) - 2400)
-
-/* TX Power */
-#define NRF51_RADIO_TXPOWER_POS_4_DBM                 0x04
-#define NRF51_RADIO_TXPOWER_0_DBM                     0x00
-#define NRF51_RADIO_TXPOWER_NEG_8_DBM                 0xFC
-#define NRF51_RADIO_TXPOWER_NEG_12_DBM                0xF8
-#define NRF51_RADIO_TXPOWER_NEG_16_DBM                0xF4
-#define NRF51_RADIO_TXPOWER_NEG_20_DBM                0xEC
-#define NRF51_RADIO_TXPOWER_NEG_30_DBM                0xD8
-
-/* TX Mode */
-#define NRF51_RADIO_MODE_BLE_1MBIT                    0x03
-
-/*
- * PCNF0 and PCNF1 Packet Configuration
- *
- * The radio unpacks the packet for you according to these settings.
- *
- * The on-air format is:
- *
- * |_Preamble_|___Base___|_Prefix_|___S0____|_Length_,_S1_|__Payload__|___|
- * 0           <ba_bytes> <1 byte><s0_bytes>   <1 byte>    <max_bytes> <extra>
- *
- * The in-memory format is
- *
- * uint8_t s0[s0_bytes];
- * uint8_t length;
- * uint8_t s1;
- * uint8_t payload[max_bytes];
- *
- * lf_bits is how many bits to store in length
- * s1_bits is how many bits to store in s1
- *
- * If any one of these lengths are set to zero, the field is omitted in memory.
- */
-
-#define NRF51_RADIO_PCNF0_LFLEN_SHIFT                 0
-#define NRF51_RADIO_PCNF0_S0LEN_SHIFT                 8
-#define NRF51_RADIO_PCNF0_S1LEN_SHIFT                 16
-
-#define NRF51_RADIO_PCNF0_VAL(lf_bits, s0_bytes, s1_bits) \
-	((lf_bits) << NRF51_RADIO_PCNF0_LFLEN_SHIFT | \
-	 (s0_bytes) << NRF51_RADIO_PCNF0_S0LEN_SHIFT | \
-	 (s1_bits) << NRF51_RADIO_PCNF0_S1LEN_SHIFT)
-
-#define NRF51_RADIO_PCNF1_MAXLEN_SHIFT                0
-#define NRF51_RADIO_PCNF1_STATLEN_SHIFT               8
-#define NRF51_RADIO_PCNF1_BALEN_SHIFT                 16
-#define NRF51_RADIO_PCNF1_ENDIAN_BIG                  0x1000000
-#define NRF51_RADIO_PCNF1_WHITEEN                     0x2000000
-
-#define NRF51_RADIO_PCNF1_VAL(max_bytes, extra_bytes, ba_bytes, whiten) \
-	((max_bytes) << NRF51_RADIO_PCNF1_MAXLEN_SHIFT | \
-	 (extra_bytes) << NRF51_RADIO_PCNF1_STATLEN_SHIFT | \
-	 (ba_bytes) << NRF51_RADIO_PCNF1_BALEN_SHIFT | \
-	 ((whiten) ? NRF51_RADIO_PCNF1_WHITEEN : 0))
-
-/* PREFIX0 */
-#define NRF51_RADIO_PREFIX0_AP0_SHIFT                 0
-#define NRF51_RADIO_PREFIX0_AP1_SHIFT                 8
-#define NRF51_RADIO_PREFIX0_AP2_SHIFT                 16
-#define NRF51_RADIO_PREFIX0_AP3_SHIFT                 24
-
-/* PREFIX1 */
-#define NRF51_RADIO_PREFIX1_AP4_SHIFT                 0
-#define NRF51_RADIO_PREFIX1_AP5_SHIFT                 8
-#define NRF51_RADIO_PREFIX1_AP6_SHIFT                 16
-#define NRF51_RADIO_PREFIX1_AP7_SHIFT                 24
-
-/* CRCCNF */
-#define NRF51_RADIO_CRCCNF_SKIP_ADDR                  0x100
-
-/* TEST */
-#define NRF51_RADIO_TEST_CONST_CARRIER_EN             0x01
-#define NRF51_RADIO_TEST_PLL_LOCK_EN                  0x02
-
-/* STATE */
-#define NRF51_RADIO_STATE_DISABLED                    0
-#define NRF51_RADIO_STATE_RXRU                        1
-#define NRF51_RADIO_STATE_RXIDLE                      2
-#define NRF51_RADIO_STATE_RX                          3
-#define NRF51_RADIO_STATE_RXDISABLE                   4
-#define NRF51_RADIO_STATE_TXRU                        9
-#define NRF51_RADIO_STATE_TXIDLE                      10
-#define NRF51_RADIO_STATE_TX                          11
-#define NRF51_RADIO_STATE_TXDISABLE                   12
-
-/* DACNF */
-#define NRF51_RADIO_DACNF_ENA(n)                      (1 << (n))
-#define NRF51_RADIO_DACNF_MAX                         8
-#define NRF51_RADIO_DACNF_TXADD(n)                    (1 << ((n)+8))
-#define NRF51_RADIO_TXADD_MAX                         8
-
-/* OVERRIDE4 */
-#define NRF51_RADIO_OVERRIDE_EN                       BIT(31)
-
-
-/*
- *  UART
- */
-#define NRF51_UART_BASE     0x40002000
-/* Tasks */
-#define NRF51_UART_STARTRX  REG32(NRF51_UART_BASE + 0x000)
-#define NRF51_UART_STOPRX   REG32(NRF51_UART_BASE + 0x004)
-#define NRF51_UART_STARTTX  REG32(NRF51_UART_BASE + 0x008)
-#define NRF51_UART_STOPTX   REG32(NRF51_UART_BASE + 0x00C)
-/* Events */
-#define NRF51_UART_RXDRDY   REG32(NRF51_UART_BASE + 0x108)
-#define NRF51_UART_TXDRDY   REG32(NRF51_UART_BASE + 0x11C)
-#define NRF51_UART_ERROR    REG32(NRF51_UART_BASE + 0x124)
-#define NRF51_UART_RXTO     REG32(NRF51_UART_BASE + 0x144)
-/* Registers */
-#define NRF51_UART_INTENSET REG32(NRF51_UART_BASE + 0x304)
-#define NRF51_UART_INTENCLR REG32(NRF51_UART_BASE + 0x308)
-#define NRF51_UART_ERRORSRC REG32(NRF51_UART_BASE + 0x480)
-#define NRF51_UART_ENABLE   REG32(NRF51_UART_BASE + 0x500)
-#define NRF51_UART_PSELRTS  REG32(NRF51_UART_BASE + 0x508)
-#define NRF51_UART_PSELTXD  REG32(NRF51_UART_BASE + 0x50C)
-#define NRF51_UART_PSELCTS  REG32(NRF51_UART_BASE + 0x510)
-#define NRF51_UART_PSELRXD  REG32(NRF51_UART_BASE + 0x514)
-#define NRF51_UART_RXD      REG32(NRF51_UART_BASE + 0x518)
-#define NRF51_UART_TXD      REG32(NRF51_UART_BASE + 0x51C)
-#define NRF51_UART_BAUDRATE REG32(NRF51_UART_BASE + 0x524)
-#define NRF51_UART_CONFIG   REG32(NRF51_UART_BASE + 0x56C)
-/* For UART.INTEN bits */
-#define NRF55_UART_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_UART_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instances
- */
-#define NRF51_TWI_BASE(port)     (0x40003000 + ((port == 0) ? 0 : 0x1000))
-/* Tasks */
-#define NRF51_TWI_STARTRX(port)   REG32(NRF51_TWI_BASE(port) + 0x000)
-#define NRF51_TWI_STARTTX(port)   REG32(NRF51_TWI_BASE(port) + 0x008)
-#define NRF51_TWI_STOP(port)      REG32(NRF51_TWI_BASE(port) + 0x014)
-#define NRF51_TWI_SUSPEND(port)   REG32(NRF51_TWI_BASE(port) + 0x01C)
-#define NRF51_TWI_RESUME(port)    REG32(NRF51_TWI_BASE(port) + 0x020)
-/* Events */
-#define NRF51_TWI_STOPPED(port)   REG32(NRF51_TWI_BASE(port) + 0x104)
-#define NRF51_TWI_RXDRDY(port)    REG32(NRF51_TWI_BASE(port) + 0x108)
-#define NRF51_TWI_TXDSENT(port)   REG32(NRF51_TWI_BASE(port) + 0x11C)
-#define NRF51_TWI_ERROR(port)     REG32(NRF51_TWI_BASE(port) + 0x124)
-#define NRF51_TWI_BB(port)        REG32(NRF51_TWI_BASE(port) + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI_INTEN(port)     REG32(NRF51_TWI_BASE(port) + 0x300)
-#define NRF51_TWI_INTENSET(port)  REG32(NRF51_TWI_BASE(port) + 0x304)
-#define NRF51_TWI_INTENCLR(port)  REG32(NRF51_TWI_BASE(port) + 0x308)
-#define NRF51_TWI_ERRORSRC(port)  REG32(NRF51_TWI_BASE(port) + 0x4C4)
-#define NRF51_TWI_ENABLE(port)    REG32(NRF51_TWI_BASE(port) + 0x500)
-#define NRF51_TWI_PSELSCL(port)   REG32(NRF51_TWI_BASE(port) + 0x508)
-#define NRF51_TWI_PSELSDA(port)   REG32(NRF51_TWI_BASE(port) + 0x50C)
-#define NRF51_TWI_RXD(port)       REG32(NRF51_TWI_BASE(port) + 0x518)
-#define NRF51_TWI_TXD(port)       REG32(NRF51_TWI_BASE(port) + 0x51C)
-#define NRF51_TWI_FREQUENCY(port) REG32(NRF51_TWI_BASE(port) + 0x524)
-#define NRF51_TWI_ADDRESS(port)   REG32(NRF51_TWI_BASE(port) + 0x588)
-#define NRF51_TWI_POWER(port)     REG32(NRF51_TWI_BASE(port) + 0xFFC)
-
-#define NRF51_TWI_100KBPS         0x01980000
-#define NRF51_TWI_250KBPS         0x40000000
-#define NRF51_TWI_400KBPS         0x06680000
-
-#define NRF51_TWI_ENABLE_VAL      0x5
-#define NRF51_TWI_DISABLE_VAL     0x0
-
-#define NRF51_TWI_ERRORSRC_ANACK  BIT(1) /* Address NACK */
-#define NRF51_TWI_ERRORSRC_DNACK  BIT(2) /* Data NACK */
-
-/*
- *  TWI (I2C) Instance 0
- */
-#define NRF51_TWI0_BASE     0x40003000
-/* Tasks */
-#define NRF51_TWI0_STARTRX   REG32(NRF51_TWI0_BASE + 0x000)
-#define NRF51_TWI0_STARTTX   REG32(NRF51_TWI0_BASE + 0x008)
-#define NRF51_TWI0_STOP      REG32(NRF51_TWI0_BASE + 0x014)
-#define NRF51_TWI0_SUSPEND   REG32(NRF51_TWI0_BASE + 0x01C)
-#define NRF51_TWI0_RESUME    REG32(NRF51_TWI0_BASE + 0x020)
-/* Events */
-#define NRF51_TWI0_STOPPED   REG32(NRF51_TWI0_BASE + 0x104)
-#define NRF51_TWI0_RXDRDY    REG32(NRF51_TWI0_BASE + 0x108)
-#define NRF51_TWI0_TXDSENT   REG32(NRF51_TWI0_BASE + 0x11C)
-#define NRF51_TWI0_ERROR     REG32(NRF51_TWI0_BASE + 0x124)
-#define NRF51_TWI0_BB        REG32(NRF51_TWI0_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI0_INTENSET  REG32(NRF51_TWI0_BASE + 0x304)
-#define NRF51_TWI0_INTENCLR  REG32(NRF51_TWI0_BASE + 0x308)
-#define NRF51_TWI0_ERRORSRC  REG32(NRF51_TWI0_BASE + 0x4C4)
-#define NRF51_TWI0_ENABLE    REG32(NRF51_TWI0_BASE + 0x500)
-#define NRF51_TWI0_PSELSCL   REG32(NRF51_TWI0_BASE + 0x508)
-#define NRF51_TWI0_PSELSDA   REG32(NRF51_TWI0_BASE + 0x50C)
-#define NRF51_TWI0_RXD       REG32(NRF51_TWI0_BASE + 0x518)
-#define NRF51_TWI0_TXD       REG32(NRF51_TWI0_BASE + 0x51C)
-#define NRF51_TWI0_FREQUENCY REG32(NRF51_TWI0_BASE + 0x524)
-#define NRF51_TWI0_ADDRESS   REG32(NRF51_TWI0_BASE + 0x588)
-
-/* For TWI0.INTEN bits */
-#define NRF55_TWI0_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI0_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  TWI (I2C) Instance 1
- */
-#define NRF51_TWI1_BASE     0x40004000
-/* Tasks */
-#define NRF51_TWI1_STARTRX   REG32(NRF51_TWI1_BASE + 0x000)
-#define NRF51_TWI1_STARTTX   REG32(NRF51_TWI1_BASE + 0x008)
-#define NRF51_TWI1_STOP      REG32(NRF51_TWI1_BASE + 0x014)
-#define NRF51_TWI1_SUSPEND   REG32(NRF51_TWI1_BASE + 0x01C)
-#define NRF51_TWI1_RESUME    REG32(NRF51_TWI1_BASE + 0x020)
-/* Events */
-#define NRF51_TWI1_STOPPED   REG32(NRF51_TWI1_BASE + 0x104)
-#define NRF51_TWI1_RXDRDY    REG32(NRF51_TWI1_BASE + 0x108)
-#define NRF51_TWI1_TXDSENT   REG32(NRF51_TWI1_BASE + 0x11C)
-#define NRF51_TWI1_ERROR     REG32(NRF51_TWI1_BASE + 0x124)
-#define NRF51_TWI1_BB        REG32(NRF51_TWI1_BASE + 0x138)
-/* Registers */
-/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4)  */
-#define NRF51_TWI1_INTENSET  REG32(NRF51_TWI1_BASE + 0x304)
-#define NRF51_TWI1_INTENCLR  REG32(NRF51_TWI1_BASE + 0x308)
-#define NRF51_TWI1_ERRORSRC  REG32(NRF51_TWI1_BASE + 0x4C4)
-#define NRF51_TWI1_ENABLE    REG32(NRF51_TWI1_BASE + 0x500)
-#define NRF51_TWI1_PSELSCL   REG32(NRF51_TWI1_BASE + 0x508)
-#define NRF51_TWI1_PSELSDA   REG32(NRF51_TWI1_BASE + 0x50C)
-#define NRF51_TWI1_RXD       REG32(NRF51_TWI1_BASE + 0x518)
-#define NRF51_TWI1_TXD       REG32(NRF51_TWI1_BASE + 0x51C)
-#define NRF51_TWI1_FREQUENCY REG32(NRF51_TWI1_BASE + 0x524)
-#define NRF51_TWI1_ADDRESS   REG32(NRF51_TWI1_BASE + 0x588)
-
-/* For TWI1.INTEN bits */
-#define NRF55_TWI1_RXDRDY_BIT  ((0x108 - 0x100) / 4)
-#define NRF55_TWI1_TXDRDY_BIT  ((0x11C - 0x100) / 4)
-
-/*
- *  GPIOTE - GPIO Tasks and Events
- */
-#define NRF51_GPIOTE_BASE   0x40006000
-/* Tasks */
-#define NRF51_GPIOTE_OUT(n)    REG32(NRF51_GPIOTE_BASE + ((n) * 4))
-/* Events */
-#define NRF51_GPIOTE_IN(n)     REG32(NRF51_GPIOTE_BASE + 0x100 + ((n) * 4))
-#define NRF51_GPIOTE_PORT      REG32(NRF51_GPIOTE_BASE + 0x17C)
-/* Registers */
-#define NRF51_GPIOTE_INTENSET  REG32(NRF51_GPIOTE_BASE + 0x304)
-#define NRF51_GPIOTE_INTENCLR  REG32(NRF51_GPIOTE_BASE + 0x308)
-#define NRF51_GPIOTE_CONFIG(n) REG32(NRF51_GPIOTE_BASE + 0x510 + ((n) * 4))
-#define NRF51_GPIOTE_POWER     REG32(NRF51_GPIOTE_BASE + 0xFFC)
-
-/* Number of IN events */
-#define NRF51_GPIOTE_IN_COUNT  4
-
-/* Bits */
-/* For GPIOTE.INTEN */
-#define NRF51_GPIOTE_IN_BIT(n) (n)
-#define NRF51_GPIOTE_PORT_BIT  31
-/* For GPIOTE.CONFIG */
-#define NRF51_GPIOTE_MODE_DISABLED     (0<<0)
-#define NRF51_GPIOTE_MODE_EVENT        BIT(0)
-#define NRF51_GPIOTE_MODE_TASK         (3<<0)
-#define NRF51_GPIOTE_PSEL_POS          (8)
-#define NRF51_GPIOTE_POLARITY_LOTOHI   BIT(16)
-#define NRF51_GPIOTE_POLARITY_HITOLO   (2<<16)
-#define NRF51_GPIOTE_POLARITY_TOGGLE   (3<<16)
-#define NRF51_GPIOTE_OUTINIT_LOW       (0<<20)
-#define NRF51_GPIOTE_OUTINIT_HIGH      BIT(20)
-
-/*
- *  Timer / Counter
- */
-#define NRF51_TIMER0_BASE   0x40008000
-#define NRF51_TIMER_BASE(n)   (NRF51_TIMER0_BASE + (n) * 0x1000)
-#define NRF51_PERID_TIMER(n)  (NRF51_PERID_TIMER0 + (n))
-/* Tasks */
-#define NRF51_TIMER_START(n)  REG32(NRF51_TIMER_BASE(n) + 0x000)
-#define NRF51_TIMER_STOP(n)   REG32(NRF51_TIMER_BASE(n) + 0x004)
-#define NRF51_TIMER_COUNT(n)  REG32(NRF51_TIMER_BASE(n) + 0x008)
-#define NRF51_TIMER_CLEAR(n)  REG32(NRF51_TIMER_BASE(n) + 0x00C)
-#define NRF51_TIMER_CAPTURE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x040 + 4 * (c))
-/* Events */
-#define NRF51_TIMER_COMPARE(n, c)  REG32(NRF51_TIMER_BASE(n) + 0x140 + 4 * (c))
-/* Registers */
-#define NRF51_TIMER_SHORTCUT(n)  REG32(NRF51_TIMER_BASE(n) + 0x200)
-#define NRF51_TIMER_INTENSET(n)  REG32(NRF51_TIMER_BASE(n) + 0x304)
-#define NRF51_TIMER_INTENCLR(n)  REG32(NRF51_TIMER_BASE(n) + 0x308)
-#define NRF51_TIMER_MODE(n)      REG32(NRF51_TIMER_BASE(n) + 0x504)
-#define NRF51_TIMER_BITMODE(n)   REG32(NRF51_TIMER_BASE(n) + 0x508)
-#define NRF51_TIMER_PRESCALER(n) REG32(NRF51_TIMER_BASE(n) + 0x510)
-#define NRF51_TIMER_CC(n, c)     REG32(NRF51_TIMER_BASE(n) + 0x540 + 4 * (c))
-/* For Timer.INTEN bits */
-#define NRF51_TIMER_COMPARE_BIT(n)  (((0x140 - 0x100) / 4) + (n))
-/* For Timer Shortcuts */
-#define NRF51_TIMER_COMPARE_CLEAR(n)  (1 << (n))
-#define NRF51_TIMER_COMPARE_STOP(n)   (1 << (8 + (n)))
-/* Timer Mode (NRF51_TIMER_MODE) */
-#define NRF51_TIMER_MODE_TIMER   0  /* reset default */
-#define NRF51_TIMER_MODE_COUNTER 1
-/* Prescaler */
-#define NRF51_TIMER_PRESCALER_MASK (0xf)  /* range: 0-9, reset default: 4 */
-/* Bit length (NRF51_TIMER_BITMODE) */
-#define NRF51_TIMER_BITMODE_16  0  /* reset default */
-#define NRF51_TIMER_BITMODE_8   1
-#define NRF51_TIMER_BITMODE_24  2
-#define NRF51_TIMER_BITMODE_32  3
-
-
-/*
- *  Random Number Generator (RNG)
- */
-#define NRF51_RNG_BASE               0x4000D000
-/* Tasks */
-#define NRF51_RNG_START              REG32(NRF51_RNG_BASE + 0x000)
-#define NRF51_RNG_STOP               REG32(NRF51_RNG_BASE + 0x004)
-/* Events */
-#define NRF51_RNG_VALRDY             REG32(NRF51_RNG_BASE + 0x100)
-/* Registers */
-#define NRF51_RNG_SHORTS             REG32(NRF51_RNG_BASE + 0x200)
-#define NRF51_RNG_INTENSET           REG32(NRF51_RNG_BASE + 0x304)
-#define NRF51_RNG_INTENCLR           REG32(NRF51_RNG_BASE + 0x308)
-#define NRF51_RNG_CONFIG             REG32(NRF51_RNG_BASE + 0x504)
-#define NRF51_RNG_VALUE              REG32(NRF51_RNG_BASE + 0x508)
-/* For RNG Shortcuts */
-#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0)
-/* For RNG Config */
-#define NRF51_RNG_DERCEN             BIT(0)
-
-
-/*
- *  Watchdog Timer (WDT)
- */
-#define NRF51_WDT_BASE        0x40010000
-/* Tasks */
-#define NRF51_WDT_START       REG32(NRF51_WDT_BASE + 0x000)
-/* Events */
-#define NRF51_WDT_TIMEOUT     REG32(NRF51_WDT_BASE + 0x100)
-/* Registers */
-#define NRF51_WDT_INTENSET    REG32(NRF51_WDT_BASE + 0x304)
-#define NRF51_WDT_INTENCLR    REG32(NRF51_WDT_BASE + 0x308)
-#define NRF51_WDT_RUNSTATUS   REG32(NRF51_WDT_BASE + 0x400)
-#define NRF51_WDT_REQSTATUS   REG32(NRF51_WDT_BASE + 0x404)
-#define NRF51_WDT_CRV         REG32(NRF51_WDT_BASE + 0x504)
-#define NRF51_WDT_RREN        REG32(NRF51_WDT_BASE + 0x508)
-#define NRF51_WDT_CONFIG      REG32(NRF51_WDT_BASE + 0x50C)
-#define NRF51_WDT_RR(n)       REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4))
-#define NRF51_WDT_POWER       REG32(NRF51_WDT_BASE + 0xFFC)
-/* Bitfields */
-#define NRF51_WDT_RUNSTATUS_RUNNING        1
-#define NRF51_WDT_REQSTATUS_BIT(n)        (1<<(n))
-#define NRF51_WDT_RREN_BIT(n)             (1<<(n))
-#define NRF51_WDT_CONFIG_SLEEP_PAUSE       0
-#define NRF51_WDT_CONFIG_SLEEP_RUN         1
-#define NRF51_WDT_CONFIG_HALT_PAUSE       (0<<4)
-#define NRF51_WDT_CONFIG_HALT_RUN         BIT(4)
-
-#define NRF51_WDT_RELOAD_VAL             0x6E524635
-
-
-/*
- *  GPIO
- */
-#define NRF51_GPIO_BASE     0x50000000
-#define NRF51_GPIO0_BASE    (NRF51_GPIO_BASE + 0x500)
-#define NRF51_GPIO0_OUT     REG32(NRF51_GPIO0_BASE + 0x004)
-#define NRF51_GPIO0_OUTSET  REG32(NRF51_GPIO0_BASE + 0x008)
-#define NRF51_GPIO0_OUTCLR  REG32(NRF51_GPIO0_BASE + 0x00C)
-#define NRF51_GPIO0_IN      REG32(NRF51_GPIO0_BASE + 0x010)
-#define NRF51_GPIO0_DIR     REG32(NRF51_GPIO0_BASE + 0x014)  /* 1 for output */
-#define NRF51_GPIO0_DIRSET  REG32(NRF51_GPIO0_BASE + 0x018)
-#define NRF51_GPIO0_DIRCLR  REG32(NRF51_GPIO0_BASE + 0x01C)
-#define NRF51_PIN_BASE      (NRF51_GPIO_BASE + 0x700)
-#define NRF51_PIN_CNF(n)    REG32(NRF51_PIN_BASE + ((n) * 4))
-#define GPIO_0              NRF51_GPIO0_BASE
-
-#define NRF51_PIN_CNF_DIR_INPUT        (0)
-#define NRF51_PIN_CNF_DIR_OUTPUT       (1)
-#define NRF51_PIN_CNF_INPUT_CONNECT    (0<<1)
-#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1)
-#define NRF51_PIN_CNF_PULL_DISABLED    (0<<2)
-#define NRF51_PIN_CNF_PULLDOWN         BIT(2)
-#define NRF51_PIN_CNF_PULLUP           (3<<2)
-/*
- * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect
- * for example, S0D1 = Standard drive 0, disconnect on 1
- */
-#define NRF51_PIN_CNF_DRIVE_S0S1       (0<<8)
-#define NRF51_PIN_CNF_DRIVE_H0S1       BIT(8)
-#define NRF51_PIN_CNF_DRIVE_S0H1       (2<<8)
-#define NRF51_PIN_CNF_DRIVE_H0H1       (3<<8)
-#define NRF51_PIN_CNF_DRIVE_D0S1       (4<<8)
-#define NRF51_PIN_CNF_DRIVE_D0H1       (5<<8)
-#define NRF51_PIN_CNF_DRIVE_S0D1       (6<<8)
-#define NRF51_PIN_CNF_DRIVE_H0D1       (7<<8)
-
-#define NRF51_PIN_CNF_SENSE_DISABLED   (0<<16)
-#define NRF51_PIN_CNF_SENSE_HIGH       (2<<16)
-#define NRF51_PIN_CNF_SENSE_LOW        (3<<16)
-
-#define UNIMPLEMENTED_GPIO_BANK     GPIO_0  /* for UNIMPLEMENTED() macro */
-
-#define NRF51_PPI_BASE                 0x4001F000
-#define NRF51_PPI_CHEN                 REG32(NRF51_PPI_BASE + 0x500)
-#define NRF51_PPI_CHENSET              REG32(NRF51_PPI_BASE + 0x504)
-#define NRF51_PPI_CHENCLR              REG32(NRF51_PPI_BASE + 0x508)
-#define NRF51_PPI_EEP(channel)         REG32(NRF51_PPI_BASE + 0x510 + channel*8)
-#define NRF51_PPI_TEP(channel)         REG32(NRF51_PPI_BASE + 0x514 + channel*8)
-#define NRF51_PPI_CHG(group)           REG32(NRF51_PPI_BASE + 0x800 + group*4)
-
-#define NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS        16
-#define NRF51_PPI_NUM_GROUPS                       4
-
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN        20
-#define NRF51_PPI_CH_TIMER0_CC0__RADIO_RXEN        21
-#define NRF51_PPI_CH_TIMER0_CC1__RADIO_DISABLE     22
-#define NRF51_PPI_CH_RADIO_BCMATCH__AAR_START      23
-#define NRF51_PPI_CH_RADIO_READY__CCM_KSGEN        24
-#define NRF51_PPI_CH_RADIO_ADDR__CCM_CRYPT         25
-#define NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1         26
-#define NRF51_PPI_CH_RADIO_END_TIMER0CC2           27
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_TXEN     28
-#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_RXEN     29
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_CLEAR   30
-#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START   31
-
-#define NRF51_PPI_CH_FIRST NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN
-#define NRF51_PPI_CH_LAST  NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START
-
-
-/* These will be defined in their respective functions if/when they are used. */
-#define NRF51_SPI0_BASE       0x40003000
-#define NRF51_SPI0_PSELSCK    REG32(NRF51_SPI0_BASE + 0x508)
-#define NRF51_SPI0_PSELMOSI   REG32(NRF51_SPI0_BASE + 0x50C)
-#define NRF51_SPI0_PSELMISO   REG32(NRF51_SPI0_BASE + 0x510)
-#define NRF51_SPI1_BASE       0x40004000
-#define NRF51_SPI1_PSELSCK    REG32(NRF51_SPI1_BASE + 0x508)
-#define NRF51_SPI1_PSELMOSI   REG32(NRF51_SPI1_BASE + 0x50C)
-#define NRF51_SPI1_PSELMISO   REG32(NRF51_SPI1_BASE + 0x510)
-#define NRF51_SPIS1_BASE      0x40004000
-#define NRF51_SPIS1_PSELSCK   REG32(NRF51_SPIS1_BASE + 0x508)
-#define NRF51_SPIS1_PSELMISO  REG32(NRF51_SPIS1_BASE + 0x50C)
-#define NRF51_SPIS1_PSELMOSI  REG32(NRF51_SPIS1_BASE + 0x510)
-#define NRF51_SPIS1_PSELCSN   REG32(NRF51_SPIS1_BASE + 0x514)
-#define NRF51_QDEC_BASE       0x40012000
-#define NRF51_QDEC_PSELLED    REG32(NRF51_QDEC_BASE + 0x51C)
-#define NRF51_QDEC_PSELA      REG32(NRF51_QDEC_BASE + 0x520)
-#define NRF51_QDEC_PSELB      REG32(NRF51_QDEC_BASE + 0x524)
-#define NRF51_LPCOMP_BASE     0x40013000
-#define NRF51_LPCOMP_PSEL     REG32(NRF51_LPCOMP_BASE + 0x504)
-
-#endif /* __CROS_EC_REGISTERS_H */
-
diff --git a/chip/nrf51/system.c b/chip/nrf51/system.c
deleted file mode 100644
index dc7bff2059..0000000000
--- a/chip/nrf51/system.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* System module for Chrome EC : hardware specific implementation */
-
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "cpu.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-const char *system_get_chip_vendor(void)
-{
-	return "nrf";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "nrf51822";
-}
-
-const char *system_get_chip_revision(void)
-{
-	return "";
-}
-
-void system_hibernate(uint32_t seconds, uint32_t microseconds)
-{
-	/* Flush console before hibernating */
-	cflush();
-
-	if (board_hibernate)
-		board_hibernate();
-
-	/* chip specific standby mode */
-	CPRINTS("TODO: implement %s()", __func__);
-}
-
-
-static void check_reset_cause(void)
-{
-	uint32_t flags = 0;
-	uint32_t raw_cause = NRF51_POWER_RESETREAS;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_RESETPIN)
-		flags |= EC_RESET_FLAG_RESET_PIN;
-
-	if (raw_cause & NRF51_POWER_RESETREAS_DOG)
-		flags |= EC_RESET_FLAG_WATCHDOG;
-
-	/* Note that the programmer uses a soft reset in debug mode. */
-	if (raw_cause & NRF51_POWER_RESETREAS_SREQ)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_OFF |
-			NRF51_POWER_RESETREAS_LPCOMP))
-		flags |= EC_RESET_FLAG_WAKE_PIN;
-
-	if (raw_cause & (NRF51_POWER_RESETREAS_LOCKUP |
-			NRF51_POWER_RESETREAS_DIF))
-		flags |= EC_RESET_FLAG_OTHER;
-
-	system_set_reset_flags(flags);
-
-	/* clear it by writing 1's */
-	NRF51_POWER_RESETREAS = raw_cause;
-}
-
-static void system_watchdog_reset(void)
-{
-	if (NRF51_WDT_TIMEOUT != 0) {
-		/* Hard reset the WDT */
-		NRF51_WDT_POWER = 0;
-		NRF51_WDT_POWER = 1;
-	}
-
-	/* NRF51_WDT_CONFIG_HALT_RUN breaks this */
-	NRF51_WDT_CONFIG = NRF51_WDT_CONFIG_SLEEP_RUN;
-
-	NRF51_WDT_RREN = NRF51_WDT_RREN_BIT(0);
-	NRF51_WDT_CRV = 3; /* @32KHz */
-	NRF51_WDT_START = 1;
-}
-
-void system_reset(int flags)
-{
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-	if (flags & SYSTEM_RESET_HARD)
-		/* Ask the watchdog to trigger a hard reboot */
-		system_watchdog_reset();
-	else {
-		/* Use SYSRESETREQ to trigger a soft reboot */
-		CPU_NVIC_APINT = 0x05fa0004;
-	}
-
-	/* Spin and wait for reboot; should never return */
-	while (1)
-		;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}
-
-void system_pre_init(void)
-{
-	check_reset_cause();
-}
diff --git a/chip/nrf51/uart.c b/chip/nrf51/uart.c
deleted file mode 100644
index 1f546a2b79..0000000000
--- a/chip/nrf51/uart.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "clock.h"
-#include "console.h"
-#include "common.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-static int ever_sent;    /* if we ever sent byte to TXD? */
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
-
-int uart_init_done(void)
-{
-	return init_done;
-}
-
-void uart_tx_start(void)
-{
-	disable_sleep(SLEEP_MASK_UART);
-	should_stop = 0;
-	NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-	task_trigger_irq(NRF51_PERID_USART);
-}
-
-void uart_tx_stop(void)
-{
-	NRF51_UART_INTENCLR = BIT(NRF55_UART_TXDRDY_BIT);
-	should_stop = 1;
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * nRF51 design is NOT tx-empty style. Instead, it is if a byte is
-	 * ever transmitted from TxD. This means NRF51_UART_TXDRDY is always
-	 * 0 after reset. So, we use 'ever_sent' to send the first byte.
-	 */
-	return NRF51_UART_TXDRDY || (!ever_sent);
-}
-
-int uart_rx_available(void)
-{
-	return NRF51_UART_RXDRDY;
-}
-
-void uart_tx_flush(void)
-{
-	while (!uart_tx_ready())
-		;
-}
-
-void uart_write_char(char c)
-{
-	ever_sent = 1;
-	NRF51_UART_TXDRDY = 0;
-	NRF51_UART_TXD = c;
-	NRF51_UART_STARTTX = 1;
-}
-
-int uart_read_char(void)
-{
-	NRF51_UART_RXDRDY = 0;
-	return NRF51_UART_RXD;
-}
-
-/* Interrupt handler for console USART */
-void uart_interrupt(void)
-{
-#ifndef CONFIG_UART_RX_DMA
-	/*
-	 * Read input FIFO until empty.  DMA-based receive does this from a
-	 * hook in the UART buffering module.
-	 */
-	uart_process_input();
-#endif
-
-	/* Fill output FIFO */
-	uart_process_output();
-
-#ifndef CONFIG_UART_TX_DMA
-	if (!should_stop)
-		NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT);
-#endif  /* CONFIG_UART_TX_DMA */
-
-}
-DECLARE_IRQ(NRF51_PERID_USART, uart_interrupt, 2);
-
-
-void uart_init(void)
-{
-	NRF51_UART_PSELTXD = NRF51_UART_TX_PIN;   /* GPIO Port for Tx */
-	NRF51_UART_PSELRXD = NRF51_UART_RX_PIN;   /* GPIO Port for Rx */
-	NRF51_UART_CONFIG = 0;    /* disable HW flow control, no parity bit */
-	NRF51_UART_BAUDRATE = 0x01d7e000;  /* 115200 */
-	NRF51_UART_ENABLE = 0x4;  /* Enable UART */
-
-	task_enable_irq(NRF51_PERID_USART);
-
-	NRF51_UART_INTENSET = BIT(NRF55_UART_RXDRDY_BIT);
-	NRF51_UART_STARTRX = 1;
-
-	init_done = 1;
-}
diff --git a/chip/nrf51/watchdog.c b/chip/nrf51/watchdog.c
deleted file mode 100644
index da947df48e..0000000000
--- a/chip/nrf51/watchdog.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "console.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-
-int watchdog_init(void)
-{
-	CPRINTS("TODO: implement %s()", __func__);
-	return EC_ERROR_UNIMPLEMENTED;
-}