ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 170 deletions

diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c
deleted file mode 100644
index c1f1cfae4a..0000000000
--- a/chip/stm32/adc-stm32l.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "adc.h"
-#include "common.h"
-#include "console.h"
-#include "clock.h"
-#include "dma.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
-
-struct mutex adc_lock;
-
-static int restore_clock;
-
-static inline void adc_set_channel(int sample_id, int channel)
-{
-	uint32_t mask, val;
-	volatile uint32_t *sqr_reg;
-	int reg_id;
-
-	reg_id = 5 - sample_id / 6;
-
-	mask = 0x1f << ((sample_id % 6) * 5);
-	val = channel << ((sample_id % 6) * 5);
-	sqr_reg = &STM32_ADC_SQR(reg_id);
-
-	*sqr_reg = (*sqr_reg & ~mask) | val;
-}
-
-static void adc_configure(int ain_id)
-{
-	/* Set ADC channel */
-	adc_set_channel(0, ain_id);
-
-	/* Disable DMA */
-	STM32_ADC_CR2 &= ~BIT(8);
-
-	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~BIT(8);
-}
-
-static void adc_configure_all(void)
-{
-	int i;
-
-	/* Set ADC channels */
-	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
-	for (i = 0; i < ADC_CH_COUNT; ++i)
-		adc_set_channel(i, adc_channels[i].channel);
-
-	/* Enable DMA */
-	STM32_ADC_CR2 |= BIT(8);
-
-	/* Enable scan mode */
-	STM32_ADC_CR1 |= BIT(8);
-}
-
-static inline int adc_powered(void)
-{
-	return STM32_ADC_SR & BIT(6); /* ADONS */
-}
-
-static void adc_enable_clock(void)
-{
-	STM32_RCC_APB2ENR |= BIT(9);
-	/* ADCCLK = HSI / 2 = 8MHz*/
-	STM32_ADC_CCR |= BIT(16);
-}
-
-static void adc_init(void)
-{
-	/*
-	 * For STM32L, ADC clock source is HSI/2 = 8 MHz. HSI must be enabled
-	 * for ADC.
-	 *
-	 * Note that we are not powering on ADC on EC initialization because
-	 * STM32L ADC module requires HSI clock. Instead, ADC module is powered
-	 * on/off in adc_prepare()/adc_release().
-	 */
-
-	/* Enable ADC clock. */
-	adc_enable_clock();
-
-	if (!adc_powered())
-		/* Power on ADC module */
-		STM32_ADC_CR2 |= BIT(0);  /* ADON */
-
-	/* Set right alignment */
-	STM32_ADC_CR2 &= ~BIT(11);
-
-	/*
-	 * Set sample time of all channels to 16 cycles.
-	 * Conversion takes (12+16)/8M = 3.34 us.
-	 */
-	STM32_ADC_SMPR1 = 0x24924892;
-	STM32_ADC_SMPR2 = 0x24924892;
-	STM32_ADC_SMPR3 = 0x24924892;
-}
-
-static void adc_prepare(void)
-{
-	if (!adc_powered()) {
-		clock_enable_module(MODULE_ADC, 1);
-		adc_init();
-		restore_clock = 1;
-	}
-}
-
-static void adc_release(void)
-{
-	if (restore_clock) {
-		clock_enable_module(MODULE_ADC, 0);
-		restore_clock = 0;
-	}
-
-	/*
-	 * Power down the ADC.  The ADC consumes a non-trivial amount of power,
-	 * so it's wasteful to leave it on.
-	 */
-	if (adc_powered())
-		STM32_ADC_CR2 = 0;
-}
-
-static inline int adc_conversion_ended(void)
-{
-	return STM32_ADC_SR & BIT(1);
-}
-
-int adc_read_channel(enum adc_channel ch)
-{
-	const struct adc_t *adc = adc_channels + ch;
-	int value;
-	timestamp_t deadline;
-
-	mutex_lock(&adc_lock);
-
-	adc_prepare();
-
-	adc_configure(adc->channel);
-
-	/* Clear EOC bit */
-	STM32_ADC_SR &= ~BIT(1);
-
-	/* Start conversion */
-	STM32_ADC_CR2 |= BIT(30); /* SWSTART */
-
-	/* Wait for EOC bit set */
-	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
-	value = ADC_READ_ERROR;
-	do {
-		if (adc_conversion_ended()) {
-			value = STM32_ADC_DR & ADC_READ_MAX;
-			break;
-		}
-	} while (!timestamp_expired(deadline, NULL));
-
-	adc_release();
-
-	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
-}