Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release

Relevant changes:

git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "stm32f_rtc": PASSED
     Test "panic_data_bloonchipper_v2.0.4277": PASSED
     Test "panic_data_bloonchipper_v2.0.5938": PASSED

Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3

1 files changed, 26 insertions, 31 deletions

diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
index b0bf56d85f..dbb8fd88cb 100644
--- a/chip/stm32/clock-stm32g4.c
+++ b/chip/stm32/clock-stm32g4.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks configuration routines */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "clock-f.h"
@@ -21,14 +22,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
-#define MHZ(x) ((x) * 1000000)
-#define WAIT_STATE_FREQ_STEP_HZ	MHZ(20)
+#define MHZ(x) ((x)*1000000)
+#define WAIT_STATE_FREQ_STEP_HZ MHZ(20)
 /* PLL configuration constants */
-#define STM32G4_SYSCLK_MAX_HZ		MHZ(170)
-#define STM32G4_HSI_CLK_HZ		MHZ(16)
-#define STM32G4_PLL_IN_FREQ_HZ		MHZ(4)
+#define STM32G4_SYSCLK_MAX_HZ MHZ(170)
+#define STM32G4_HSI_CLK_HZ MHZ(16)
+#define STM32G4_PLL_IN_FREQ_HZ MHZ(4)
 #define STM32G4_PLL_R 2
 #define STM32G4_AHB_PRE 1
 #define STM32G4_APB1_PRE 1
@@ -42,7 +43,7 @@ enum rcc_clksrc {
 };
 
 static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
-			      uint32_t pll_clk_in_hz)
+			       uint32_t pll_clk_in_hz)
 {
 	/*
 	 * The pll output frequency (Fhclkc) is determined by:
@@ -81,20 +82,16 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
 	ASSERT(pll_m && (pll_m <= 16));
 	ASSERT((pll_n >= 8) && (pll_n <= 127));
 
-	hclk_freq = pll_clk_in_hz * pll_n / (pll_m *
-					      STM32G4_PLL_R * STM32G4_AHB_PRE);
+	hclk_freq = pll_clk_in_hz * pll_n /
+		    (pll_m * STM32G4_PLL_R * STM32G4_AHB_PRE);
 	/* Ensure that there aren't any integer rounding errors */
 	ASSERT(hclk_freq == hclk_hz);
 
 	/* Program PLL config register */
-	STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) |
-		PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
-		PLLCFGR_PLLR_EN |
-		PLLCFGR_PLLQ(0) |
-		PLLCFGR_PLLQ_EN |
-		PLLCFGR_PLLN(pll_n) |
-		PLLCFGR_PLLM(pll_m - 1) |
-		pll_src;
+	STM32_RCC_PLLCFGR =
+		PLLCFGR_PLLP(0) | PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
+		PLLCFGR_PLLR_EN | PLLCFGR_PLLQ(0) | PLLCFGR_PLLQ_EN |
+		PLLCFGR_PLLN(pll_n) | PLLCFGR_PLLM(pll_m - 1) | pll_src;
 
 	/* Wait until PLL is locked */
 	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON,
@@ -116,8 +113,8 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
 static void stm32g4_config_low_speed_clock(void)
 {
 	/* Ensure that LSI is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
+	wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION,
+		       STM32_RCC_CSR_LSIRDY);
 
 	/* Setup RTC Clock input */
 	STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
@@ -163,10 +160,10 @@ void stm32g4_set_flash_ws(uint32_t freq_hz)
 	 * found in Table 9 of RM0440 - STM32G4 technical reference manual. A
 	 * table lookup is not required though as WS = HCLK (MHz) / 20
 	 */
-	ws = freq_hz /  WAIT_STATE_FREQ_STEP_HZ;
+	ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ;
 	/* Enable data and instruction cache */
 	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN |
-		STM32_FLASH_ACR_PRFTEN | ws;
+			   STM32_FLASH_ACR_PRFTEN | ws;
 }
 
 void clock_init(void)
@@ -255,16 +252,14 @@ void clock_enable_module(enum module_id module, int enable)
 	} else if (module == MODULE_I2C) {
 		if (enable) {
 			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR1 |=
-				STM32_RCC_APB1ENR1_I2C1EN |
-				STM32_RCC_APB1ENR1_I2C2EN |
-				STM32_RCC_APB1ENR1_I2C3EN;
+			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_I2C1EN |
+					      STM32_RCC_APB1ENR1_I2C2EN |
+					      STM32_RCC_APB1ENR1_I2C3EN;
 			STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN;
 		} else {
-			STM32_RCC_APB1ENR1 &=
-				~(STM32_RCC_APB1ENR1_I2C1EN |
-				  STM32_RCC_APB1ENR1_I2C2EN |
-				  STM32_RCC_APB1ENR1_I2C3EN);
+			STM32_RCC_APB1ENR1 &= ~(STM32_RCC_APB1ENR1_I2C1EN |
+						STM32_RCC_APB1ENR1_I2C2EN |
+						STM32_RCC_APB1ENR1_I2C3EN);
 			STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN;
 		}
 	} else if (module == MODULE_ADC) {
@@ -274,7 +269,7 @@ void clock_enable_module(enum module_id module, int enable)
 					      STM32_RCC_APB2ENR_ADC345EN);
 		else
 			STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
+					       STM32_RCC_APB2ENR_ADC345EN);
 	} else {
 		CPRINTS("stm32g4: enable clock module %d not supported",
 			module);