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| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /chip/stm32/config-stm32h7x3.h | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-stabilize-14388.62.B-ish.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32h7x3.h')
| -rw-r--r-- | chip/stm32/config-stm32h7x3.h | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h deleted file mode 100644 index da94b09069..0000000000 --- a/chip/stm32/config-stm32h7x3.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) -#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ -/* always use 256-bit writes due to ECC */ -#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 - -/* - * What the code is calling 'bank' is really the size of the block used for - * write-protected, here it's 128KB sector (same as erase size). - */ -#define CONFIG_FLASH_BANK_SIZE (128 * 1024) - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* ITCM-RAM: 64kB 0x00000000 - 0x0000FFFF (CPU and MDMA) */ -/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF (CPU and MDMA) */ -/* (D1) AXI-SRAM : 512kB 0x24000000 - 0x2407FFFF (no BDMA) */ -/* (D2) AHB-SRAM1: 128kB 0x30000000 - 0x3001FFFF */ -/* (D2) AHB-SRAM2: 128kB 0x30020000 - 0x3003FFFF */ -/* (D2) AHB-SRAM3: 32kB 0x30040000 - 0x30047FFF */ -/* (D3) AHB-SRAM4: 64kB 0x38000000 - 0x3800FFFF */ -/* (D3) backup RAM: 4kB 0x38800000 - 0x38800FFF */ -#define CONFIG_RAM_BASE 0x24000000 -#define CONFIG_RAM_SIZE 0x00080000 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (512 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* - * Cannot use PSTATE: - * 128kB blocks are too large and ECC prevents re-writing PSTATE word. - */ -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 150 - -/* the Cortex-M7 core has 'standard' ARMv7-M caches */ -#define CONFIG_ARMV7M_CACHE -/* Use the MPU to configure cacheability */ -#define CONFIG_MPU -/* Store in uncached buffers for DMA transfers in ahb4 region */ -#define CONFIG_CHIP_UNCACHED_REGION ahb4 -/* Override MPU attribute settings to match the chip requirements */ -/* Code is Normal memory type / non-shareable / write-through */ -#define MPU_ATTR_FLASH_MEMORY 0x02 -/* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */ -#define MPU_ATTR_INTERNAL_SRAM 0x0B |