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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-01-30 17:01:50 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-02-09 05:24:47 -0800 |
| commit | 730491df202e5b14e489a5ab31a78e47fcd47af3 (patch) | |
| tree | 3bf2d703861c832769ded44e18b42df614050356 /chip/stm32/config-stm32h7x3.h | |
| parent | 4ee04e1c4a978b49e5340e475e3db185e78e4949 (diff) | |
| download | chrome-ec-730491df202e5b14e489a5ab31a78e47fcd47af3.tar.gz | |
stm32: add internal flash support for STM32H7 family
The STM32H7 family has 2 banks of flash (with 2 hardware controllers
able to do 2 parallel operations at the same time).
Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB
variants).
The flash can only be written by 256-bit word (with an additional 10-bit
ECC computed by the hardware).
For the flash write-protection, we cannot use our 'classical' PSTATE
scheme as the erase-blocks are too large (128-kB) to dedicate one to
this and the embedded word in the RO partition would not work as the
flash has ECC and triggers bus-fault when the ECC is incorrect (which
includes the case where the 256-bit word is written a second time).
So we will do the following:
- use the RSS1 bit in the option bytes as the Write-Protect enabled bit.
- if the WP GPIO is set, lock at startup the option bytes until next
reboot.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC
console.
Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6
Reviewed-on: https://chromium-review.googlesource.com/901423
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32h7x3.h')
| -rw-r--r-- | chip/stm32/config-stm32h7x3.h | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h index 9b4dde19c9..72b9bd21de 100644 --- a/chip/stm32/config-stm32h7x3.h +++ b/chip/stm32/config-stm32h7x3.h @@ -4,7 +4,17 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE (1048 * 1024) +#define CONFIG_FLASH_SIZE (2048 * 1024) +#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ +/* always use 256-bit writes due to ECC */ +#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 + +/* + * What the code is calling 'bank' is really the size of the block used for + * write-protected, here it's 128KB sector (same as erase size). + */ +#define CONFIG_FLASH_BANK_SIZE (128 * 1024) /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -22,8 +32,8 @@ #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (128 * 1024) -#define CONFIG_RW_SIZE (896 * 1024) +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2) +#define CONFIG_RW_SIZE (512 * 1024) #define CONFIG_RO_STORAGE_OFF 0 #define CONFIG_RW_STORAGE_OFF 0 @@ -40,8 +50,11 @@ #undef I2C_PORT_COUNT #define I2C_PORT_COUNT 4 -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE +/* + * Cannot use PSTATE: + * 128kB blocks are too large and ECC prevents re-writing PSTATE word. + */ +#undef CONFIG_FLASH_PSTATE #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ |