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| author | Vadim Bendebury <vbendeb@chromium.org> | 2020-01-03 15:04:15 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-07 00:17:09 +0000 |
| commit | 943645d993c88754b2db1e86734210256c505e07 (patch) | |
| tree | 45ddf3e6cb66d1943b0e4eeb6cade057247f24c5 /chip/stm32/crc_hw.h | |
| parent | c4e8fffe2024108ed4373f910a5b68291aa3802e (diff) | |
| download | chrome-ec-943645d993c88754b2db1e86734210256c505e07.tar.gz | |
drop unnecessary boards, chips and cts tests
The only board which would be built from this branch is Cr50. bds,
fizz and host boards are necessary for proper make infrastructure
operation and tests.
lm4 and npcx are chips used by the bds and fizz boards, so they are
also kept around.
BRANCH=cr50, cr50-mp
BUG=b:145912698
TEST='make buildall -j' succeeds
Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Diffstat (limited to 'chip/stm32/crc_hw.h')
| -rw-r--r-- | chip/stm32/crc_hw.h | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h deleted file mode 100644 index 2a50d5760e..0000000000 --- a/chip/stm32/crc_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CRC_HW_H -#define __CROS_EC_CRC_HW_H -/* CRC-32 hardware implementation with USB constants */ - -#include "clock.h" -#include "registers.h" - -static inline void crc32_init(void) -{ - /* switch on CRC controller */ - STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */ - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); - /* reset CRC state */ - STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT - | STM32_CRC_CR_REV_IN_WORD; - while (STM32_CRC_CR & 1) - ; -} - -static inline void crc32_hash32(uint32_t val) -{ - STM32_CRC_DR = val; -} - -static inline void crc32_hash16(uint16_t val) -{ - STM32_CRC_DR16 = val; -} - -static inline uint32_t crc32_result(void) -{ - return STM32_CRC_DR ^ 0xFFFFFFFF; -} - -#endif /* __CROS_EC_CRC_HW_H */ |