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| author | Scott Collyer <scollyer@google.com> | 2020-07-27 18:30:24 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-29 03:49:04 +0000 |
| commit | dea20bc5f83286287abfd3c219391f44a2e5122a (patch) | |
| tree | 157d8168a489dc35eac7049fe23ccb46a99f7e79 /chip/stm32/registers-stm32g4.h | |
| parent | 08df256be2e54d3d9655d100f8a2b68c9a21590f (diff) | |
| download | chrome-ec-dea20bc5f83286287abfd3c219391f44a2e5122a.tar.gz | |
stm32g4: Fix issue with APB1 base address
The initial version of this file had a cut/paste error. Fixing the
base address for APB1 bus
BUG=148493929
BRANCH=None
TEST=make BOARD=quiche is successful
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I5c2abc0342bde4a66f166f87971617110c5acfd5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324403
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/registers-stm32g4.h')
| -rw-r--r-- | chip/stm32/registers-stm32g4.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h index 4d0b09c7be..ee7fd7e7ea 100644 --- a/chip/stm32/registers-stm32g4.h +++ b/chip/stm32/registers-stm32g4.h @@ -117,7 +117,7 @@ /* Peripheral base addresses */ #define STM32_PERIPH_BASE (0x40000000UL) /* Peripheral memory map */ -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) +#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL) #define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL) #define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL) |