diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2017-08-13 13:16:38 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-08-18 16:46:34 -0700 |
| commit | 3cbdff8b1bc3f8621a1c6801340c45b0951aee17 (patch) | |
| tree | c9585128735c06d6d6cf94ebe066ca21f2f021c8 /chip/stm32/registers.h | |
| parent | b6d83d456f0293f329c34c5005c578d87a7cf7cc (diff) | |
| download | chrome-ec-3cbdff8b1bc3f8621a1c6801340c45b0951aee17.tar.gz | |
stm32: add embryonic support for STM32F76x
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 918afaf974..bfe5b7321c 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -213,7 +213,7 @@ #define STM32_USART_REG(base, offset) REG32((base) + (offset)) #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) + defined(CHIP_FAMILY_STM32L4) || defined(CHIP_VARIANT_STM32F76X) #define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) #define STM32_USART_CR1_UE (1 << 0) #define STM32_USART_CR1_UESM (1 << 1) @@ -417,6 +417,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define GPIO_ALT_TIM9_11 0x3 #define GPIO_ALT_I2C 0x4 #define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 #define GPIO_ALT_USART 0x7 #define GPIO_ALT_I2C_23 0x9 #define GPIO_ALT_USB 0xA @@ -962,6 +963,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK +#define STM32F4_PLLP_DIV 4 #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 @@ -977,6 +979,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) +#define STM32F4_PLLP_DIV 4 #define STM32F4_AHB_PRE 0x0 #define STM32F4_APB1_PRE 0x4 #define STM32F4_APB2_PRE 0x4 @@ -992,11 +995,28 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK +#define STM32F4_PLLP_DIV 4 #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 #define STM32_FLASH_ACR_LATENCY (1 << 0) +#elif defined(CHIP_VARIANT_STM32F76X) +/* Required or recommended clocks for stm32f767/769 */ +#define STM32F4_PLL_REQ 2000000 +#define STM32F4_RTC_REQ 1000000 +#define STM32F4_IO_CLOCK 45000000 +#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ +#define STM32F4_VCO_CLOCK 360000000 +#define STM32F4_HSI_CLOCK 16000000 +#define STM32F4_LSI_CLOCK 32000 +#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) +#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ +#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ +#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ +#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ +#define STM32_FLASH_ACR_LATENCY (5 << 0) + #else #error "No valid clocks defined" #endif @@ -1214,7 +1234,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; /* --- SPI --- */ #define STM32_SPI1_BASE 0x40013000 #define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373 and STM32L4 */ +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ /* The SPI controller registers */ struct stm32_spi_regs { @@ -1872,7 +1892,7 @@ enum dma_channel { /* Legacy naming for uart.c */ STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, -#if defined(CHIP_VARIANT_STM32F411) +#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F76X) STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6, STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5, @@ -1881,7 +1901,7 @@ enum dma_channel { STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX, #endif -#if defined(CHIP_VARIANT_STM32F411) +#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F76X) STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1, STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, @@ -1909,6 +1929,8 @@ enum dma_channel { STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ + STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ + STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ }; @@ -1934,6 +1956,8 @@ enum dma_channel { #define STM32_SPI1_RX_REQ_CH 3 #define STM32_SPI2_TX_REQ_CH 0 #define STM32_SPI2_RX_REQ_CH 0 +#define STM32_SPI3_TX_REQ_CH 0 +#define STM32_SPI3_RX_REQ_CH 0 #define STM32_DMAS_TOTAL_COUNT 16 |