ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 172 deletions

diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c
deleted file mode 100644
index 7f8c55aaa6..0000000000
--- a/chip/stm32/usart.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* USART driver for Chrome EC */
-
-#include "atomic.h"
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "usart.h"
-#include "util.h"
-
-void usart_init(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-	uint32_t cr2, cr3;
-
-	/*
-	 * Enable clock to USART, this must be done first, before attempting
-	 * to configure the USART.
-	 */
-	*(config->hw->clock_register) |= config->hw->clock_enable;
-
-	/*
-	 * For STM32F3, A delay of 1 APB clock cycles is needed before we
-	 * can access any USART register. Fortunately, we have
-	 * gpio_config_module() below and thus don't need to add the delay.
-	 */
-
-	/*
-	 * Switch all GPIOs assigned to the USART module over to their USART
-	 * alternate functions.
-	 */
-	gpio_config_module(MODULE_USART, 1);
-
-	/*
-	 * 8N1, 16 samples per bit. error interrupts, and special modes
-	 * disabled.
-	 */
-
-	cr2 = 0x0000;
-	cr3 = 0x0000;
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-    defined(CHIP_FAMILY_STM32L4)
-	if (config->flags & USART_CONFIG_FLAG_RX_INV)
-		cr2 |= BIT(16);
-	if (config->flags & USART_CONFIG_FLAG_TX_INV)
-		cr2 |= BIT(17);
-#endif
-	if (config->flags & USART_CONFIG_FLAG_HDSEL)
-		cr3 |= BIT(3);
-
-	STM32_USART_CR1(base) = 0x0000;
-	STM32_USART_CR2(base) = cr2;
-	STM32_USART_CR3(base) = cr3;
-
-	/*
-	 * Enable the RX, TX, and variant specific HW.
-	 */
-	config->rx->init(config);
-	config->tx->init(config);
-	config->hw->ops->enable(config);
-
-	/*
-	 * Clear error counts.
-	 */
-	config->state->rx_overrun = 0;
-	config->state->rx_dropped = 0;
-
-	/*
-	 * Enable the USART, this must be done last since most of the
-	 * configuration bits require that the USART be disabled for writes to
-	 * succeed.
-	 */
-	STM32_USART_CR1(base) |= STM32_USART_CR1_UE;
-}
-
-void usart_shutdown(struct usart_config const *config)
-{
-	STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_UE;
-
-	config->hw->ops->disable(config);
-}
-
-void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz)
-{
-	int      div  = DIV_ROUND_NEAREST(frequency_hz, baud);
-	intptr_t base = config->hw->base;
-
-	if (div / 16 > 0) {
-		/*
-		 * CPU clock is high enough to support x16 oversampling.
-		 * BRR = (div mantissa)<<4 | (4-bit div fraction)
-		 */
-		STM32_USART_CR1(base) &= ~STM32_USART_CR1_OVER8;
-		STM32_USART_BRR(base) = div;
-	} else {
-		/*
-		 * CPU clock is low; use x8 oversampling.
-		 * BRR = (div mantissa)<<4 | (3-bit div fraction)
-		 */
-		STM32_USART_BRR(base) = ((div / 8) << 4) | (div & 7);
-		STM32_USART_CR1(base) |= STM32_USART_CR1_OVER8;
-	}
-}
-
-void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz)
-{
-	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
-
-	/* STM32F only supports x16 oversampling */
-	STM32_USART_BRR(config->hw->base) = div;
-}
-
-int usart_get_parity(struct usart_config const *config)
-{
-	intptr_t base = config->hw->base;
-
-	if (!(STM32_USART_CR1(base) & STM32_USART_CR1_PCE))
-		return 0;
-	if (STM32_USART_CR1(base) & STM32_USART_CR1_PS)
-		return 1;
-	return 2;
-}
-
-/*
- * We only allow 8 bit word. CR1_PCE modifies parity enable,
- * CR1_PS modifies even/odd, CR1_M modifies total word length
- * to make room for parity.
- */
-void usart_set_parity(struct usart_config const *config, int parity)
-{
-	uint32_t ue;
-	intptr_t base = config->hw->base;
-
-	if ((parity < 0) || (parity > 2))
-		return;
-
-	/* Record active state and disable the UART. */
-	ue = STM32_USART_CR1(base) & STM32_USART_CR1_UE;
-	STM32_USART_CR1(base) &= ~STM32_USART_CR1_UE;
-
-	if (parity) {
-		/* Set parity control enable. */
-		STM32_USART_CR1(base) |=
-			(STM32_USART_CR1_PCE | STM32_USART_CR1_M);
-		/* Set parity select even/odd bit. */
-		if (parity == 2)
-			STM32_USART_CR1(base) &= ~STM32_USART_CR1_PS;
-		else
-			STM32_USART_CR1(base) |= STM32_USART_CR1_PS;
-	} else {
-		STM32_USART_CR1(base) &=
-			~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS |
-			  STM32_USART_CR1_M);
-	}
-
-	/* Restore active state. */
-	STM32_USART_CR1(base) |= ue;
-}
-
-void usart_interrupt(struct usart_config const *config)
-{
-	config->tx->interrupt(config);
-	config->rx->interrupt(config);
-}