ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 147 deletions

diff --git a/common/onewire.c b/common/onewire.c
deleted file mode 100644
index cdb5837255..0000000000
--- a/common/onewire.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* 1-wire interface module for Chrome EC */
-
-#include "common.h"
-#include "gpio.h"
-#include "task.h"
-#include "timer.h"
-
-/*
- * Standard speed; all timings padded by 2 usec for safety.
- *
- * Note that these timing are actually _longer_ than legacy 1-wire standard
- * speed because we're running the 1-wire bus at 3.3V instead of 5V.
- */
-#define T_RSTL 602  /* Reset low pulse; 600-960 us */
-#define T_MSP   72  /* Presence detect sample time; 70-75 us */
-#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin */
-#define T_SLOT  70  /* Timeslot; >67 us */
-#define T_W0L   63  /* Write 0 low; 62-120 us */
-#define T_W1L    7  /* Write 1 low; 5-15 us */
-#define T_RL     7  /* Read low; 5-15 us */
-#define T_MSR    9  /* Read sample time; <15 us.  Must be at least 200 ns after
-		     * T_RL since that's how long the signal takes to be pulled
-		     * up on our board.  */
-
-/**
- * Output low on the bus for <usec> us, then switch back to open-drain input.
- */
-static void output0(int usec)
-{
-	gpio_set_flags(GPIO_ONEWIRE,
-		       GPIO_OPEN_DRAIN | GPIO_OUTPUT | GPIO_OUT_LOW);
-	udelay(usec);
-	gpio_set_flags(GPIO_ONEWIRE, GPIO_INPUT);
-}
-
-/**
- * Read a bit.
- */
-static int readbit(void)
-{
-	int bit;
-
-	/*
-	 * The delay between sending the output pulse and reading the bit is
-	 * extremely timing sensitive, so disable interrupts.
-	 */
-	interrupt_disable();
-
-	/* Output low */
-	output0(T_RL);
-
-	/*
-	 * Delay to let peripheral release the line if it wants to send
-	 * a 1-bit
-	 */
-	udelay(T_MSR - T_RL);
-
-	/* Read bit */
-	bit = gpio_get_level(GPIO_ONEWIRE);
-
-	/*
-	 * Enable interrupt as soon as we've read the bit.  The delay to the
-	 * end of the timeslot is a lower bound, so additional latency here is
-	 * harmless.
-	 */
-	interrupt_enable();
-
-	/* Delay to end of timeslot */
-	udelay(T_SLOT - T_MSR);
-	return bit;
-}
-
-/**
- * Write a bit.
- */
-static void writebit(int bit)
-{
-	/*
-	 * The delays in the output-low signal for sending 0 and 1 bits are
-	 * extremely timing sensitive, so disable interrupts during that time.
-	 * Interrupts can be enabled again as soon as the output is switched
-	 * back to open-drain, since the delay for the rest of the timeslot is
-	 * a lower bound.
-	 */
-	if (bit) {
-		interrupt_disable();
-		output0(T_W1L);
-		interrupt_enable();
-		udelay(T_SLOT - T_W1L);
-	} else {
-		interrupt_disable();
-		output0(T_W0L);
-		interrupt_enable();
-		udelay(T_SLOT - T_W0L);
-	}
-
-}
-
-int onewire_reset(void)
-{
-	/* Start transaction with controller reset pulse */
-	output0(T_RSTL);
-
-	/* Wait for presence detect sample time.
-	 *
-	 * (Alternately, we could poll waiting for a 1-bit indicating our pulse
-	 * has let go, then poll up to max time waiting for a 0-bit indicating
-	 * the peripheral has responded.)
-	 */
-	udelay(T_MSP);
-
-	if (gpio_get_level(GPIO_ONEWIRE))
-		return EC_ERROR_UNKNOWN;
-
-	/*
-	 * Wait for end of presence pulse.
-	 *
-	 * (Alternately, we could poll waiting for a 1-bit.)
-	 */
-	udelay(T_RSTH - T_MSP);
-
-	return EC_SUCCESS;
-}
-
-int onewire_read(void)
-{
-	int data = 0;
-	int i;
-
-	for (i = 0; i < 8; i++)
-		data |= readbit() << i;  /* LSB first */
-
-	return data;
-}
-
-void onewire_write(int data)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		writebit((data >> i) & 0x01);  /* LSB first */
-}