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| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /core/cortex-m/cache.S | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-stabilize-14588.98.B-ish.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'core/cortex-m/cache.S')
| -rw-r--r-- | core/cortex-m/cache.S | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S deleted file mode 100644 index 0a3d3bb67d..0000000000 --- a/core/cortex-m/cache.S +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * ARMv7-M architectural caches maintenance operations. - */ - -.syntax unified -.text -.thumb - -/* System Control Block: cache registers */ -#define SCB_CCSIDR 0xe000ed80 -#define SCB_CCSELR 0xe000ed84 -#define SCB_DCISW 0xe000ef60 -#define SCB_DCCISW 0xe000ef74 - -.macro dcache_set_way_op name register -@ -@ Perform an operation on all D-cache sets/ways. -@ -@ Note: implemented in assembly to guarantee that we are not touching the -@ D-cache in the middle of the loop. -@ -.thumb_func -.section .text.\name -.global \name -\name: - /* Select Level-1 Data cache (for operations on CCSIDR). */ - ldr r1, =SCB_CCSELR - movs r0, #0 - ldr r2, =SCB_CCSIDR - str r0, [r1] /* set CCSELR = 0 */ - - /* Ensure the CCSELR write is effective before reading CCSIDR. */ - dsb - /* CCSIDR contains the cache geometry. */ - ldr r3, [r2] /* [27:13] Number of sets -1 [12:3] Number of ways -1 */ - - /* register used to do the set/way cache operation. */ - ldr r0, =\register - /* r2 is the number of cache 'sets' - 1 */ - ubfx r2, r3, #13, #15 - /* r12 is the number of cache 'ways' - 1 */ - ubfx r12, r3, #3, #10 - -1: - mov r1, r12 /* reset way index */ -2: - /* - * Build address Set/Way operation e.g DC(C)ISW - * [31:30] way index [13:5] set index - */ - lsls r3, r2, #5 /* set index */ - /* TODO(crbug.com/848704) remove cache geometry assumptions */ - orr r3, r3, r1, lsl #30 /* way index */ - /* Perform operation (e.g invalidate) on a D-cache line */ - str r3, [r0] - /* go to previous way */ - subs r1, #1 - bcs 2b - /* go to previous set */ - subs r2, #1 - bcs 1b - - /* Ensure everything has propagated and return. */ - dsb - isb - bx lr -.endm - -/* D-cache Invalidate by set-way */ -dcache_set_way_op cpu_invalidate_dcache SCB_DCISW - -/* D-cache Clean and Invalidate by set-way, to Point of Coherency */ -dcache_set_way_op cpu_clean_invalidate_dcache SCB_DCCISW |