diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /core/cortex-m/cpu.c | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-stabilize-14526.73.B-ish.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'core/cortex-m/cpu.c')
| -rw-r--r-- | core/cortex-m/cpu.c | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c deleted file mode 100644 index 7c31892c18..0000000000 --- a/core/cortex-m/cpu.c +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Set up the Cortex-M core - */ - -#include "common.h" -#include "cpu.h" -#include "hooks.h" - -void cpu_init(void) -{ - /* Catch divide by 0 and unaligned access */ - CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP | CPU_NVIC_CCR_UNALIGN_TRAP; - - /* Enable reporting of memory faults, bus faults and usage faults */ - CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA | - CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA; -} - -#ifdef CONFIG_ARMV7M_CACHE -static void cpu_invalidate_icache(void) -{ - /* - * Invalidates the entire instruction cache to the point of - * unification. - */ - CPU_SCB_ICIALLU = 0; - asm volatile("dsb; isb"); -} - -void cpu_enable_caches(void) -{ - /* Check whether the I-cache is already enabled */ - if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_ICACHE)) { - /* Invalidate the I-cache first */ - cpu_invalidate_icache(); - /* Turn on the caching */ - CPU_NVIC_CCR |= CPU_NVIC_CCR_ICACHE; - asm volatile("dsb; isb"); - } - /* Check whether the D-cache is already enabled */ - if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_DCACHE)) { - /* Invalidate the D-cache first */ - cpu_invalidate_dcache(); - /* Turn on the caching */ - CPU_NVIC_CCR |= CPU_NVIC_CCR_DCACHE; - asm volatile("dsb; isb"); - } -} - -void cpu_disable_caches(void) -{ - /* - * Disable the I-cache and the D-cache - * The I-cache will be invalidated after the reboot/sysjump if needed - * (e.g after a flash update). - */ - cpu_clean_invalidate_dcache(); - CPU_NVIC_CCR &= ~(CPU_NVIC_CCR_ICACHE | CPU_NVIC_CCR_DCACHE); - asm volatile("dsb; isb"); -} -DECLARE_HOOK(HOOK_SYSJUMP, cpu_disable_caches, HOOK_PRIO_LAST); -#endif /* CONFIG_ARMV7M_CACHE */ |