Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release

Relevant changes:

git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "stm32f_rtc": PASSED
     Test "panic_data_bloonchipper_v2.0.4277": PASSED
     Test "panic_data_bloonchipper_v2.0.5938": PASSED

Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3

1 files changed, 75 insertions, 67 deletions

diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index e3137cd864..8c284d6132 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,68 +10,69 @@
 
 #include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
-#define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              BIT(0)
-#define ST_TICKINT             BIT(1)
-#define ST_CLKSOURCE           BIT(2)
-#define ST_COUNTFLAG           BIT(16)
+#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010)
+#define ST_ENABLE BIT(0)
+#define ST_TICKINT BIT(1)
+#define ST_CLKSOURCE BIT(2)
+#define ST_COUNTFLAG BIT(16)
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180 + 4 * (x))
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280 + 4 * (x))
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10))
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0xFA05U << 16)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_PRIOGRP (BIT(8) | BIT(9) | BIT(10))
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* NVIC STIR : Software Trigger Interrupt Register */
-#define CPU_NVIC_SWTRIG        CPUREG(0xe000ef00)
+#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
 
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
-#define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
-#define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
-#define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
-#define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
+#define CPU_NVIC_CFSR CPUREG(0xe000ed28)
+#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
+#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
+#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
+#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
 
 enum {
-	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
-	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
+	CPU_NVIC_CFSR_BFARVALID = BIT(15),
+	CPU_NVIC_CFSR_MFARVALID = BIT(7),
 
-	CPU_NVIC_CCR_ICACHE		= BIT(17),
-	CPU_NVIC_CCR_DCACHE		= BIT(16),
-	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
-	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
+	CPU_NVIC_CCR_ICACHE = BIT(17),
+	CPU_NVIC_CCR_DCACHE = BIT(16),
+	CPU_NVIC_CCR_DIV_0_TRAP = BIT(4),
+	CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3),
 
-	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= BIT(30),
-	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
+	CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
+	CPU_NVIC_HFSR_FORCED = BIT(30),
+	CPU_NVIC_HFSR_VECTTBL = BIT(1),
 
-	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
-	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
-	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
+	CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16),
+	CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17),
+	CPU_NVIC_SHCSR_USGFAULTENA = BIT(18),
 };
 
 /* System Control Block: cache registers */
-#define CPU_SCB_CCSIDR         CPUREG(0xe000ed80)
-#define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
-#define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
-#define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
+#define CPU_SCB_CCSIDR CPUREG(0xe000ed80)
+#define CPU_SCB_CCSELR CPUREG(0xe000ed84)
+#define CPU_SCB_ICIALLU CPUREG(0xe000ef50)
+#define CPU_SCB_DCISW CPUREG(0xe000ef60)
+#define CPU_SCB_DCCISW CPUREG(0xe000ef74)
 
 /* Floating Point Context Address Register */
-#define CPU_FPU_FPCAR          CPUREG(0xe000ef38)
+#define CPU_FPU_FPCAR CPUREG(0xe000ef38)
 
 /*
  * As defined by Armv7-M Reference Manual B1.5.7 "Context state stacking on
@@ -85,28 +86,29 @@ enum {
 #define FPU_FPSCR_UFC BIT(3) /* Underflow */
 #define FPU_FPSCR_IXC BIT(4) /* Inexact */
 #define FPU_FPSCR_IDC BIT(7) /* Input denormal */
-#define FPU_FPSCR_EXC_FLAGS (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | \
-			     FPU_FPSCR_UFC | FPU_FPSCR_IXC | FPU_FPSCR_IDC)
+#define FPU_FPSCR_EXC_FLAGS                                              \
+	(FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | FPU_FPSCR_UFC | \
+	 FPU_FPSCR_IXC | FPU_FPSCR_IDC)
 
 /* Bitfield values for EXC_RETURN. */
-#define EXC_RETURN_ES_MASK	BIT(0)
+#define EXC_RETURN_ES_MASK BIT(0)
 #define EXC_RETURN_ES_NON_SECURE 0
-#define EXC_RETURN_ES_SECURE	BIT(0)
-#define EXC_RETURN_SPSEL_MASK	BIT(2)
-#define EXC_RETURN_SPSEL_MSP	0
-#define EXC_RETURN_SPSEL_PSP	BIT(2)
-#define EXC_RETURN_MODE_MASK	BIT(3)
-#define EXC_RETURN_MODE_HANDLER	0
-#define EXC_RETURN_MODE_THREAD	BIT(3)
-#define EXC_RETURN_FTYPE_MASK	BIT(4)
-#define EXC_RETURN_FTYPE_ON	0
-#define EXC_RETURN_FTYPE_OFF	BIT(4)
-#define EXC_RETURN_DCRS_MASK	BIT(5)
-#define EXC_RETURN_DCRS_OFF	0
-#define EXC_RETURN_DCRS_ON	BIT(5)
-#define EXC_RETURN_S_MASK	BIT(6)
-#define EXC_RETURN_S_NON_SECURE	0
-#define EXC_RETURN_S_SECURE	BIT(6)
+#define EXC_RETURN_ES_SECURE BIT(0)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
+#define EXC_RETURN_FTYPE_MASK BIT(4)
+#define EXC_RETURN_FTYPE_ON 0
+#define EXC_RETURN_FTYPE_OFF BIT(4)
+#define EXC_RETURN_DCRS_MASK BIT(5)
+#define EXC_RETURN_DCRS_OFF 0
+#define EXC_RETURN_DCRS_ON BIT(5)
+#define EXC_RETURN_S_MASK BIT(6)
+#define EXC_RETURN_S_NON_SECURE 0
+#define EXC_RETURN_S_SECURE BIT(6)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
@@ -132,10 +134,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 7)
 		priority = 7;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(7 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(7 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */