ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 103 deletions

diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
deleted file mode 100644
index 0b03302bfc..0000000000
--- a/core/cortex-m/cpu.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers map and definitions for Cortex-MLM4x processor
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-#include <stdint.h>
-#include "compile_time_macros.h"
-
-/* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
-
-#define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              BIT(0)
-#define ST_TICKINT             BIT(1)
-#define ST_CLKSOURCE           BIT(2)
-#define ST_COUNTFLAG           BIT(16)
-
-/* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180 + 4 * (x))
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280 + 4 * (x))
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
-/* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10))
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0xFA05U << 16)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
-/* NVIC STIR : Software Trigger Interrupt Register */
-#define CPU_NVIC_SWTRIG        CPUREG(0xe000ef00)
-/* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
-
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
-#define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
-#define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
-#define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
-#define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
-
-enum {
-	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
-	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
-
-	CPU_NVIC_CCR_ICACHE		= BIT(17),
-	CPU_NVIC_CCR_DCACHE		= BIT(16),
-	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
-	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
-
-	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= BIT(30),
-	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
-
-	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
-	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
-	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
-};
-
-/* System Control Block: cache registers */
-#define CPU_SCB_CCSIDR         CPUREG(0xe000ed80)
-#define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
-#define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
-#define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
-
-/* Set up the cpu to detect faults */
-void cpu_init(void);
-/* Enable the CPU I-cache and D-cache if they are not already enabled */
-void cpu_enable_caches(void);
-/* Disable the CPU I-cache and D-cache */
-void cpu_disable_caches(void);
-/* Invalidate the D-cache */
-void cpu_invalidate_dcache(void);
-/* Clean and Invalidate the D-cache to the Point of Coherency */
-void cpu_clean_invalidate_dcache(void);
-
-/* Invalidate a single range of the D-cache */
-void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length);
-/* Clean and Invalidate a single range of the D-cache */
-void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length);
-
-/* Set the priority of the given IRQ in the NVIC (0 is highest). */
-static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
-{
-	const uint32_t prio_shift = irq % 4 * 8 + 5;
-
-	if (priority > 7)
-		priority = 7;
-
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(7 << prio_shift)) |
-		(priority << prio_shift);
-}
-
-#endif /* __CROS_EC_CPU_H */