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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /core/cortex-m/debug.h
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-14526.67.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'core/cortex-m/debug.h')
-rw-r--r--core/cortex-m/debug.h37
1 files changed, 0 insertions, 37 deletions
diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h
deleted file mode 100644
index ae5ef08d06..0000000000
--- a/core/cortex-m/debug.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_DEBUG_H
-#define __CROS_EC_DEBUG_H
-
-#include "common.h"
-#include "stdbool.h"
-
-/* For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR"
- * in the ARMv6-M Architecture Reference Manual.
- *
- * For other Cortex-M, see
- * "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M
- * Architecture Reference Manual or
- * https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register.
- */
-#define CPU_DHCSR REG32(0xE000EDF0)
-#define DHCSR_C_DEBUGEN BIT(0)
-#define DHCSR_C_HALT BIT(1)
-#define DHCSR_C_STEP BIT(2)
-#define DHCSR_C_MASKINTS BIT(3)
-#ifndef CHIP_CORE_CORTEX_M0
-#define DHCSR_C_SNAPSTALL BIT(5) /* Not available on Cortex-M0 */
-#endif
-#define DHCSR_S_REGRDY BIT(16)
-#define DHCSR_S_HALT BIT(17)
-#define DHCSR_S_SLEEP BIT(18)
-#define DHCSR_S_LOCKUP BIT(19)
-#define DHCSR_S_RETIRE_ST BIT(24)
-#define DHCSR_S_RESET_ST BIT(25)
-
-bool debugger_is_connected(void);
-
-#endif /* __CROS_EC_DEBUG_H */