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| author | Ethan Huang <ethan.huang@stmicro.corp-partner.google.com> | 2021-07-01 16:54:39 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-27 07:13:50 +0000 |
| commit | b011985e89d9d2e6fceb8ca4dc91bfb8fea52e3d (patch) | |
| tree | 1797742e33c100bdb41d5c9c5f843ff0b6cf7ad0 /core/cortex-m/ec.lds.S | |
| parent | 9694458b3be38ff440067b263c768007bb3223b5 (diff) | |
| download | chrome-ec-b011985e89d9d2e6fceb8ca4dc91bfb8fea52e3d.tar.gz | |
cortex-m/ec.lds.S: Add padding to manage RW image size
For CONFIG_FLASH_WRITE_SIZE > 4 (8 in the case of STM32L431
used in Munna), RW image size is not always 8-byte alignment which
leads to the failure from flash_range_ok and therefore
"EC sync update RW proecess" fails.
Here is the proposal of RW image size alignment with
CONFIG_FLASH_WRITE_SIZE.
1. Add output section .rw_image_size_alignment for padding
2. Expose new __image_size for hash afterward
3. Make output senction .rw_image_size_alignment
!CONFIG_CHIP_INIT_ROM_REGION guarded
BRANCH=main
BUG=b:188117811
TEST=make buildall + checking symbols (execpt __image_size) listed in
ec.R{O,R}.smap for all boards stay the same
Change-Id: Iaa3c91ded178455bde6baddbaf8abbd639d9e416
Signed-off-by: Ethan Huang <ethan.huang@stmicro.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999357
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'core/cortex-m/ec.lds.S')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index c2c3ea12a3..7b08be81a6 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -500,7 +500,18 @@ SECTIONS */ __flash_used = FLASH_USED_END - ORIGIN(EC_IMAGE_LMA_MEM_REGION); #ifndef CONFIG_CHIP_INIT_ROM_REGION +#if !(defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 4)) __image_size = __flash_used; +#else + .rw_image_size_alignment : + { + . = ORIGIN(FLASH) + __flash_used; + BYTE(0xFF); + . = ALIGN (CONFIG_FLASH_WRITE_SIZE); + } > FLASH = 0xFF + + __image_size = __flash_used + SIZEOF(.rw_image_size_alignment); +#endif #endif /* CONFIG_CHIP_INIT_ROM_REGION */ #ifdef CONFIG_FLASH_CROS |