Add Cortex-M0 core support

The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.

Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

1 files changed, 35 insertions, 0 deletions

diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S
new file mode 100644
index 0000000000..1229988d9f
--- /dev/null
+++ b/core/cortex-m0/thumb_case.S
@@ -0,0 +1,35 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Thumb mode toolchain helpers for compact switch/case statement.
+ */
+
+#include "config.h"
+
+.text
+
+.syntax unified
+.code 16
+
+/*
+ * Helper for compact switch
+ *
+ * r0: the table index
+ * lr: the table base address
+ *
+ * r0 and lr must be PRESERVED.
+ * r12 can be clobbered.
+ */
+.global __gnu_thumb1_case_uqi
+.thumb_func
+__gnu_thumb1_case_uqi:
+        push    {r1}
+        mov     r1, lr
+        lsrs    r1, r1, #1
+        lsls    r1, r1, #1
+        ldrb    r1, [r1, r0]
+        lsls    r1, r1, #1
+        add     lr, lr, r1
+        pop     {r1}
+        bx      lr