diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:43:03 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-29 07:52:05 +0000 |
| commit | 2d8ee17cd5da4d63763cdea824f4b17170cd1a2f (patch) | |
| tree | 9c32ddfe863829c7d574cdf52874e7e4846fc3e4 /core/cortex-m0 | |
| parent | 037a83444dd938098b0f103da7e324a531bdaa05 (diff) | |
| download | chrome-ec-2d8ee17cd5da4d63763cdea824f4b17170cd1a2f.tar.gz | |
core/cortex-m0/cpu.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: Iaf6ec8c57eb942ea0f884dd78c1ef2b87fcb29e4
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729829
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'core/cortex-m0')
| -rw-r--r-- | core/cortex-m0/cpu.h | 50 |
1 files changed, 24 insertions, 26 deletions
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index c30095fd65..48abf916d6 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -12,39 +12,39 @@ #include "compile_time_macros.h" /* Macro to access 32-bit registers */ -#define CPUREG(addr) (*(volatile uint32_t*)(addr)) +#define CPUREG(addr) (*(volatile uint32_t *)(addr)) /* Nested Vectored Interrupt Controller */ -#define CPU_NVIC_EN(x) CPUREG(0xe000e100) -#define CPU_NVIC_DIS(x) CPUREG(0xe000e180) -#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) -#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) -#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +#define CPU_NVIC_EN(x) CPUREG(0xe000e100) +#define CPU_NVIC_DIS(x) CPUREG(0xe000e180) +#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) +#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) /* System Control Block */ -#define CPU_SCB_ICSR CPUREG(0xe000ed04) +#define CPU_SCB_ICSR CPUREG(0xe000ed04) /* SCB AIRCR : Application interrupt and reset control register */ -#define CPU_NVIC_APINT CPUREG(0xe000ed0c) -#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ -#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ -#define CPU_NVIC_APINT_KEY_RD (0U) -#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) +#define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0U) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) /* SCB SCR : System Control Register */ -#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) -#define CPU_NVIC_CCR CPUREG(0xe000ed14) -#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c) -#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20) +#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) +#define CPU_NVIC_CCR CPUREG(0xe000ed14) +#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c) +#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20) #define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3) /* Bitfield values for EXC_RETURN. */ -#define EXC_RETURN_SPSEL_MASK BIT(2) -#define EXC_RETURN_SPSEL_MSP 0 -#define EXC_RETURN_SPSEL_PSP BIT(2) -#define EXC_RETURN_MODE_MASK BIT(3) -#define EXC_RETURN_MODE_HANDLER 0 -#define EXC_RETURN_MODE_THREAD BIT(3) +#define EXC_RETURN_SPSEL_MASK BIT(2) +#define EXC_RETURN_SPSEL_MSP 0 +#define EXC_RETURN_SPSEL_PSP BIT(2) +#define EXC_RETURN_MODE_MASK BIT(3) +#define EXC_RETURN_MODE_HANDLER 0 +#define EXC_RETURN_MODE_THREAD BIT(3) /* Set up the cpu to detect faults */ void cpu_init(void); @@ -57,10 +57,8 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority) if (priority > 3) priority = 3; - CPU_NVIC_PRI(irq / 4) = - (CPU_NVIC_PRI(irq / 4) & - ~(3 << prio_shift)) | - (priority << prio_shift); + CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(3 << prio_shift)) | + (priority << prio_shift); } #endif /* __CROS_EC_CPU_H */ |