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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /core/nds32/cpu.h
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-14526.73.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'core/nds32/cpu.h')
-rw-r--r--core/nds32/cpu.h70
1 files changed, 0 insertions, 70 deletions
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
deleted file mode 100644
index 3bd5a93efc..0000000000
--- a/core/nds32/cpu.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Registers map and definitions for Andes cores
- */
-
-#ifndef __CROS_EC_CPU_H
-#define __CROS_EC_CPU_H
-
-/*
- * This is the space required by both irq_x_ and __switch_task to store all
- * of the caller and callee registers for each task context before switching.
- */
-#define TASK_SCRATCHPAD_SIZE (18)
-
-/* Process Status Word bits */
-#define PSW_GIE BIT(0) /* Global Interrupt Enable */
-#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
-#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/* write Process Status Word privileged register */
-static inline void set_psw(uint32_t val)
-{
- asm volatile ("mtsr %0, $PSW" : : "r"(val));
-}
-
-/* read Process Status Word privileged register */
-static inline uint32_t get_psw(void)
-{
- uint32_t ret;
- asm volatile ("mfsr %0, $PSW" : "=r"(ret));
- return ret;
-}
-
-/* write Interruption Program Counter privileged register */
-static inline void set_ipc(uint32_t val)
-{
- asm volatile ("mtsr %0, $IPC" : : "r"(val));
-}
-
-/* read Interruption Program Counter privileged register */
-static inline uint32_t get_ipc(void)
-{
- uint32_t ret;
- asm volatile ("mfsr %0, $IPC" : "=r"(ret));
- return ret;
-}
-
-/* read Interruption Type privileged register */
-static inline uint32_t get_itype(void)
-{
- uint32_t ret;
- asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
- return ret;
-}
-
-/* Generic CPU core initialization */
-void cpu_init(void);
-
-extern uint32_t ilp;
-extern uint32_t ec_reset_lp;
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_CPU_H */