diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2016-06-07 10:02:02 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-14 22:00:58 -0700 |
| commit | 43552fb3f596573e0c633ad20fb313c21ddb281f (patch) | |
| tree | 51e58abbf6a2b62f589b972b6c34e7fce1a6d564 /core | |
| parent | 4bb0efcc28d5c13721867f0bca1bfd3db68268b4 (diff) | |
| download | chrome-ec-43552fb3f596573e0c633ad20fb313c21ddb281f.tar.gz | |
it83xx: Support different PLL frequencies setting (24/48/96 MHz)
Default setting is at 48MHz.
For PLL frequency at 24MHz:
1. USB module can't work, it requires 48MHz to work.
2. SSPI clock frequency is divide by two.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. uart, i2c, timer, and pd modules are function normally
at different PLL frequency settings.
2. use 'flashrom' utility to flash EC binary with different
PLL settings.
Change-Id: Iabce4726baff493a6136136af18732b58df45d7f
Reviewed-on: https://chromium-review.googlesource.com/347551
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/nds32/cpu.c | 8 | ||||
| -rw-r--r-- | core/nds32/ec.lds.S | 5 |
2 files changed, 5 insertions, 8 deletions
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c index 7a8a043656..3db4be3f19 100644 --- a/core/nds32/cpu.c +++ b/core/nds32/cpu.c @@ -11,14 +11,6 @@ void cpu_init(void) { /* DLM initialization is done in init.S */ - - uint32_t image_type = (uint32_t)cpu_init; - - /* To change interrupt vector base if at RW image */ - if (image_type > CONFIG_RW_MEM_OFF) - /* Interrupt Vector Table Base Address, in 64k Byte unit */ - IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF; - /* Global interrupt enable */ asm volatile ("setgie.e"); } diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 0d91c6d6e4..adff240325 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -40,6 +40,11 @@ SECTIONS . = ALIGN(CONFIG_IT83XX_ILM_BLOCK_SIZE); __flash_dma_start = .; KEEP(*(.flash_direct_map)) + . = ALIGN(16); + KEEP(*(.ram_code)) + __flash_dma_size = . - __flash_dma_start; + ASSERT((__flash_dma_size < CONFIG_IT83XX_ILM_BLOCK_SIZE), + "__flash_dma_size < CONFIG_IT83XX_ILM_BLOCK_SIZE"); . = ALIGN(CONFIG_IT83XX_ILM_BLOCK_SIZE); } > FLASH . = ALIGN(4); |