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| author | Aseda Aboagye <aaboagye@google.com> | 2015-10-12 13:21:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-13 21:58:01 -0700 |
| commit | 9ed620f04bf7ba4593e45e2688194f56a796c984 (patch) | |
| tree | 78495173f53798abcc247c658814ef8190ae6837 /core | |
| parent | 3dcd8f6e3adbd463e9c643f08352d916d5f87089 (diff) | |
| download | chrome-ec-9ed620f04bf7ba4593e45e2688194f56a796c984.tar.gz | |
system: Add support to reclaim space from loader.
Certain ECs which cannot load both the RO and RW images into memory
simultaneously have a little firmware (LFW) loader that is loaded into
the beginning of the program memory. This loader is responsible for
loading the RO/RW images, however once we begin executing code from
main(), the loader has already completed it's purpose. We can reuse
this space by allocating portions of the .bss section here. This
currently saves us 3k for mec1322. This section is .bss.slow.
To use this feature simply define the following config option in
board.h.
#define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW
In some cases, such as the mec1322, this region of RAM is optimized for
code and not data. Therefore, ideally infrequently used data should go
into this region.
BUG=chrome-os-partner:46056
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Flash GLaDOS; sysjump rw; Verify that we are in rw; sysjump ro;
Verify we are back in ro.
TEST=Build GLaDOS, check output memory map for LDR_REGION and .bss.slow
section.
TEST=make -j buildall tests
Change-Id: I5b95cacc211278cf780a857b5a2ecfc1a0a28c45
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/305254
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index 3e026331fe..f778ca8f88 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -36,6 +36,11 @@ MEMORY IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE #ifdef CONFIG_EXTERNAL_STORAGE +#ifdef CONFIG_REPLACE_LOADER_WITH_BSS_SLOW + LDR_REGION(rw) : \ + ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + CONFIG_LOADER_MEM_OFF, \ + LENGTH = CONFIG_LOADER_SIZE +#endif /* defined(CONFIG_REPLACE_LOADER_WITH_BSS_SLOW) */ CDRAM (rx) : \ ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(SECTION), \ LENGTH = FW_SIZE(SECTION) @@ -221,6 +226,16 @@ SECTIONS . = ALIGN(4); __bss_end = .; } > IRAM + + .bss.slow : { + /* Region of RAM reclaimed from the little firmware(LFW). */ + *(.bss.slow) +#ifdef CONFIG_REPLACE_LOADER_WITH_BSS_SLOW + } > LDR_REGION +#else + } > IRAM +#endif /* defined(CONFIG_REPLACE_LOADER_WITH_BSS_SLOW) */ + #ifdef CONFIG_EXTERNAL_STORAGE .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)) { #else |