diff options
| author | Craig Hesling <hesling@chromium.org> | 2020-01-06 13:42:05 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-13 20:30:06 +0000 |
| commit | af0a64cc36072d283149ea40967cdc3ce71cf52a (patch) | |
| tree | ee40d54dc3ba04be8249addcd9c3c8be2c189681 /core | |
| parent | 27142308bed998ea0ba0881778c7a9deb21eac5b (diff) | |
| download | chrome-ec-af0a64cc36072d283149ea40967cdc3ce71cf52a.tar.gz | |
core/system: Extract and doc cortex const
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=make BOARD=nucleo-h743zi
# Reboot H743 into bootloader using boot0 pin and reset
# Flash nucleo over FTDI and STM32 bootloader
stm32mon -u -U -w build/nucleo-h743zi/ec.bin -d /dev/ttyUSB0 -b 115200
# Reset without boot0
# Open console
minicom -D/dev/ttyACM0
reboot soft
# Verify soft reset was used
reboot hard
# Verify hard reboot was used
Change-Id: If211198b853ad97cb96b39c063d3e04bfce68179
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988232
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/cpu.h | 9 | ||||
| -rw-r--r-- | core/cortex-m0/cpu.h | 4 |
2 files changed, 12 insertions, 1 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index 47c7d0bca1..4cef402f85 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -25,9 +25,16 @@ #define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) #define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x)) #define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +/* SCB AIRCR : Application interrupt and reset control register */ #define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10)) +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) +/* NVIC STIR : Software Trigger Interrupt Register */ #define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) - +/* SCB SCR : System Control Register */ #define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) #define CPU_NVIC_CCR CPUREG(0xe000ed14) diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index 71c0ce495d..ba27c1bc82 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -26,6 +26,10 @@ /* SCB AIRCR : Application interrupt and reset control register */ #define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0U) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) /* SCB SCR : System Control Register */ #define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) #define CPU_NVIC_CCR CPUREG(0xe000ed14) |