ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 107 deletions

diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h
deleted file mode 100644
index 7a7ed6b7da..0000000000
--- a/driver/gyro_l3gd20h.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* L3GD20H gyro module for Chrome EC */
-
-#ifndef __CROS_EC_GYRO_L3GD20H_H
-#define __CROS_EC_GYRO_L3GD20H_H
-
-#include "accelgyro.h"
-#include "task.h"
-
-/*
- * 7-bit address is 110101Xb. Where 'X' is determined
- * by the voltage on the ADDR pin.
- */
-#define L3GD20_ADDR0_FLAGS       0x6a
-#define L3GD20_ADDR1_FLAGS       0x6b
-
-/* who am I  */
-#define L3GD20_WHO_AM_I          0xd7
-
-/* Chip specific registers. */
-#define L3GD20_WHO_AM_I_REG      0x0f
-#define L3GD20_CTRL_REG1         0x20
-#define L3GD20_CTRL_REG2         0x21
-#define L3GD20_CTRL_REG3         0x22
-#define L3GD20_CTRL_REG4         0x23
-#define L3GD20_CTRL_REG5         0x24
-#define L3GD20_CTRL_REFERENCE    0x25
-#define L3GD20_OUT_TEMP          0x26
-#define L3GD20_STATUS_REG        0x27
-#define L3GD20_OUT_X_L           0x28
-#define L3GD20_OUT_X_H           0x29
-#define L3GD20_OUT_Y_L           0x2a
-#define L3GD20_OUT_Y_H           0x2b
-#define L3GD20_OUT_Z_L           0x2c
-#define L3GD20_OUT_Z_H           0x2d
-#define L3GD20_FIFO_CTRL_REG     0x2e
-#define L3GD20_FIFO_SRC_REG      0x2f
-#define L3GD20_INT1_CFG          0x30
-#define L3GD20_INT1_SRC          0x31
-#define L3GD20_INT1_TSH_XH       0x32
-#define L3GD20_INT1_TSH_XL       0x33
-#define L3GD20_INT1_TSH_YH       0x34
-#define L3GD20_INT1_TSH_YL       0x35
-#define L3GD20_INT1_TSH_ZH       0x36
-#define L3GD20_INT1_TSH_ZL       0x37
-#define L3GD20_INT1_DURATION     0x38
-#define L3GD20_LOW_ODR           0x39
-
-#define L3GD20_DPS_SEL_245       (0 << 4)
-#define L3GD20_DPS_SEL_500       BIT(4)
-#define L3GD20_DPS_SEL_2000_0    (2 << 4)
-#define L3GD20_DPS_SEL_2000_1    (3 << 4)
-
-#define L3GD20_ODR_PD            (0 << 3)
-#define L3GD20_ODR_12_5HZ        (0 << 6)
-#define L3GD20_ODR_25HZ          BIT(6)
-#define L3GD20_ODR_50HZ_0        (2 << 6)
-#define L3GD20_ODR_50HZ_1        (3 << 6)
-#define L3GD20_ODR_100HZ         (0 << 6)
-#define L3GD20_ODR_200HZ         BIT(6)
-#define L3GD20_ODR_400HZ         (2 << 6)
-#define L3GD20_ODR_800HZ         (3 << 6)
-
-#define L3GD20_ODR_MASK          (3 << 6)
-#define L3GD20_STS_ZYXDA_MASK    BIT(3)
-#define L3GD20_RANGE_MASK        (3 << 4)
-#define L3GD20_LOW_ODR_MASK      BIT(0)
-#define L3GD20_ODR_PD_MASK       BIT(3)
-
-/* Min and Max sampling frequency in mHz */
-#define L3GD20_GYRO_MIN_FREQ     12500
-#define L3GD20_GYRO_MAX_FREQ     \
-	MOTION_MAX_SENSOR_FREQUENCY(800000, L3GD20_GYRO_MIN_FREQ)
-
-/*
- * Register      : STATUS_REG
- * Address       : 0X27
- */
-enum l3gd20_status {
-	L3GD20_STS_DOWN          = 0x00,
-	L3GD20_STS_ZYXDA_UP      = 0x08,
-};
-
-/*
- * Register      : CTRL_REG4
- * Address       : 0X23
- * Bit Group Name: BDU
- */
-enum l3gd20_bdu {
-	L3GD20_BDU_DISABLE       = 0x00,
-	L3GD20_BDU_ENABLE        = 0x80,
-};
-
-/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define L3GD20_RESOLUTION        16
-
-extern const struct accelgyro_drv l3gd20h_drv;
-struct l3gd20_data {
-	struct accelgyro_saved_data_t base;
-	int16_t offset[3];
-};
-
-#endif /* __CROS_EC_GYRO_L3GD20H_H */