summaryrefslogtreecommitdiff
path: root/driver/pmic_bd99992gw.h
diff options
context:
space:
mode:
authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /driver/pmic_bd99992gw.h
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-14526.57.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'driver/pmic_bd99992gw.h')
-rw-r--r--driver/pmic_bd99992gw.h31
1 files changed, 0 insertions, 31 deletions
diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h
deleted file mode 100644
index e00ea1d252..0000000000
--- a/driver/pmic_bd99992gw.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ROHM BD99992GW PMIC register map.
- */
-
-#ifndef __CROS_EC_PMIC_BD99992GW_H
-#define __CROS_EC_PMIC_BD99992GW_H
-
-#include "temp_sensor/bd99992gw.h"
-
-#define BD99992GW_REG_PWRSRCINT 0x04
-#define BD99992GW_REG_RESETIRQ1 0x08
-#define BD99992GW_REG_PBCONFIG 0x14
-#define BD99992GW_REG_PWRSTAT1 0x16
-#define BD99992GW_REG_PWRSTAT2 0x17
-#define BD99992GW_REG_VCCIOCNT 0x30
-#define BD99992GW_REG_V5ADS3CNT 0x31
-#define BD99992GW_REG_V18ACNT 0x34
-#define BD99992GW_REG_V100ACNT 0x37
-#define BD99992GW_REG_V085ACNT 0x38
-#define BD99992GW_REG_VRMODECTRL 0x3b
-#define BD99992GW_REG_DISCHGCNT1 0x3c
-#define BD99992GW_REG_DISCHGCNT2 0x3d
-#define BD99992GW_REG_DISCHGCNT3 0x3e
-#define BD99992GW_REG_DISCHGCNT4 0x3f
-#define BD99992GW_REG_SDWNCTRL 0x49
-#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */
-
-#endif /* __CROS_EC_PMIC_BD99992GW_H */