Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release

Relevant changes:

git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "stm32f_rtc": PASSED
     Test "panic_data_bloonchipper_v2.0.4277": PASSED
     Test "panic_data_bloonchipper_v2.0.5938": PASSED

Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3

1 files changed, 55 insertions, 55 deletions

diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h
index d5f6723818..d489b3d8e6 100644
--- a/driver/retimer/anx7483.h
+++ b/driver/retimer/anx7483.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,12 +20,12 @@
  * 1   DP_EN (0: disable DP mode; 1: Enable DP mode.)
  * 0   USB_EN (1: disable USB mode; 1: enable USB mode.)
  */
-#define ANX7483_ANALOG_STATUS_CTRL_REG	0x07
-#define ANX7483_CTRL_REG_BYPASS_EN	BIT(5)
-#define ANX7483_CTRL_REG_EN		BIT(4)
-#define ANX7483_CTRL_FLIP_EN		BIT(2)
-#define ANX7483_CTRL_DP_EN		BIT(1)
-#define ANX7483_CTRL_USB_EN		BIT(0)
+#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07
+#define ANX7483_CTRL_REG_BYPASS_EN BIT(5)
+#define ANX7483_CTRL_REG_EN BIT(4)
+#define ANX7483_CTRL_FLIP_EN BIT(2)
+#define ANX7483_CTRL_DP_EN BIT(1)
+#define ANX7483_CTRL_USB_EN BIT(0)
 
 /*
  * Register_EQ/FG/SW_EN register
@@ -34,8 +34,8 @@
  * 7:1 Reserved
  * 0   Reg_EQ/FG/SW_EN (0: from pin control; 1: from register control)
  */
-#define ANX7483_ENABLE_EQ_FLAT_SWING_REG	0x15
-#define ANX7483_ENABLE_EQ_FLAT_SWING_EN		BIT(0)
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15
+#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0)
 
 /*
  * EQ Settings Registers
@@ -43,20 +43,20 @@
  * 7:4 Equilation settings when pin is input
  * 3:0 Fine tuning EQ step
  */
-#define ANX7483_UTX1_PORT_CFG0_REG	0x52
-#define ANX7483_UTX2_PORT_CFG0_REG	0x16
-#define ANX7483_URX1_PORT_CFG0_REG	0x3E
-#define ANX7483_URX2_PORT_CFG0_REG	0x2A
-#define ANX7483_DRX1_PORT_CFG0_REG	0x5C
-#define ANX7483_DRX2_PORT_CFG0_REG	0x20
+#define ANX7483_UTX1_PORT_CFG0_REG 0x52
+#define ANX7483_UTX2_PORT_CFG0_REG 0x16
+#define ANX7483_URX1_PORT_CFG0_REG 0x3E
+#define ANX7483_URX2_PORT_CFG0_REG 0x2A
+#define ANX7483_DRX1_PORT_CFG0_REG 0x5C
+#define ANX7483_DRX2_PORT_CFG0_REG 0x20
 
-#define ANX7483_CFG0_EQ_SHIFT		4
-#define ANX7483_CFG0_EQ_MASK		GENMASK(7, 4)
+#define ANX7483_CFG0_EQ_SHIFT 4
+#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4)
 
 /*
  * Default CFG0 value to apply: 9.2 dB with optimized tuning step
  */
-#define ANX7483_CFG0_DEF		0x53
+#define ANX7483_CFG0_DEF 0x53
 
 /*
  * Flat Gain Settings Registers
@@ -65,17 +65,17 @@
  * 5:4 Flat gain settings when pin is input
  * 3:0 Fine tuning EQ
  */
-#define ANX7483_UTX1_PORT_CFG2_REG	0x54
-#define ANX7483_UTX2_PORT_CFG2_REG	0x18
-#define ANX7483_URX1_PORT_CFG2_REG	0x40
-#define ANX7483_URX2_PORT_CFG2_REG	0x2C
-#define ANX7483_DRX1_PORT_CFG2_REG	0x5E
-#define ANX7483_DRX2_PORT_CFG2_REG	0x22
+#define ANX7483_UTX1_PORT_CFG2_REG 0x54
+#define ANX7483_UTX2_PORT_CFG2_REG 0x18
+#define ANX7483_URX1_PORT_CFG2_REG 0x40
+#define ANX7483_URX2_PORT_CFG2_REG 0x2C
+#define ANX7483_DRX1_PORT_CFG2_REG 0x5E
+#define ANX7483_DRX2_PORT_CFG2_REG 0x22
 
 /*
  * Default CFG2 value to apply: 0.3 dB with optimized fine tuning
  */
-#define ANX7483_CFG2_DEF		0xEE
+#define ANX7483_CFG2_DEF 0xEE
 
 /*
  * Swing and 60K Input Termination Registers
@@ -85,20 +85,20 @@
  * 3:2 Vendor internal use
  * 1:0 Swing setting when configured as input port
  */
-#define ANX7483_UTX1_PORT_CFG4_REG	0x56
-#define ANX7483_UTX2_PORT_CFG4_REG	0x1A
-#define ANX7483_URX1_PORT_CFG4_REG	0x42
-#define ANX7483_URX2_PORT_CFG4_REG	0x2E
-#define ANX7483_DRX1_PORT_CFG4_REG	0x60
-#define ANX7483_DRX2_PORT_CFG4_REG	0x24
-#define ANX7483_DTX1_PORT_CFG4_REG	0x4C
-#define ANX7483_DTX2_PORT_CFG4_REG	0x38
+#define ANX7483_UTX1_PORT_CFG4_REG 0x56
+#define ANX7483_UTX2_PORT_CFG4_REG 0x1A
+#define ANX7483_URX1_PORT_CFG4_REG 0x42
+#define ANX7483_URX2_PORT_CFG4_REG 0x2E
+#define ANX7483_DRX1_PORT_CFG4_REG 0x60
+#define ANX7483_DRX2_PORT_CFG4_REG 0x24
+#define ANX7483_DTX1_PORT_CFG4_REG 0x4C
+#define ANX7483_DTX2_PORT_CFG4_REG 0x38
 
 /*
  * Default values: 1300 mV gain with 60k termination either enabled or disabled
  */
-#define ANX7483_CFG4_TERM_DISABLE	0x63
-#define ANX7483_CFG4_TERM_ENABLE	0x73
+#define ANX7483_CFG4_TERM_DISABLE 0x63
+#define ANX7483_CFG4_TERM_ENABLE 0x73
 
 /*
  * Termination Resistance Registers
@@ -108,21 +108,21 @@
  * 1   Enable termination res for UTX2 path. (0:disable 1: enable.)
  * 0   Tune Flat Gain.
  */
-#define ANX7483_UTX1_PORT_CFG3_REG	0x55
-#define ANX7483_UTX2_PORT_CFG3_REG	0x19
-#define ANX7483_URX1_PORT_CFG3_REG	0x41
-#define ANX7483_URX2_PORT_CFG3_REG	0x2D
-#define ANX7483_DTX1_PORT_CFG3_REG	0x4B
-#define ANX7483_DTX2_PORT_CFG3_REG	0x37
-#define ANX7483_DRX1_PORT_CFG3_REG	0x5F
-#define ANX7483_DRX2_PORT_CFG3_REG	0x23
+#define ANX7483_UTX1_PORT_CFG3_REG 0x55
+#define ANX7483_UTX2_PORT_CFG3_REG 0x19
+#define ANX7483_URX1_PORT_CFG3_REG 0x41
+#define ANX7483_URX2_PORT_CFG3_REG 0x2D
+#define ANX7483_DTX1_PORT_CFG3_REG 0x4B
+#define ANX7483_DTX2_PORT_CFG3_REG 0x37
+#define ANX7483_DRX1_PORT_CFG3_REG 0x5F
+#define ANX7483_DRX2_PORT_CFG3_REG 0x23
 
 /*
  * Default values: Either 100Ohm or 90Ohm, input or output
  */
-#define ANX7483_CFG3_100Ohm_IN		0x3A
-#define ANX7483_CFG3_90Ohm_IN		0x7A
-#define ANX7483_CFG3_90Ohm_OUT		0x7E
+#define ANX7483_CFG3_100Ohm_IN 0x3A
+#define ANX7483_CFG3_90Ohm_IN 0x7A
+#define ANX7483_CFG3_90Ohm_OUT 0x7E
 
 /*
  * AUX_Snooping_CTRL register
@@ -131,13 +131,13 @@
  * 2:1 AUX_VTH (00:60mVppd, 01:90mVppd, 10:120mVppd, 11:140mVppd)
  * 0   AUX_Snooping_EN (0: disable; 1: enable.)
  */
-#define ANX7483_AUX_SNOOPING_CTRL_REG	0x13
+#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13
 
 /*
  * Default value: Enable snooping with 90mVppd
  * (register ignored outside DP mode and does not need to be cleared)
  */
-#define ANX7483_AUX_SNOOPING_DEF	0x13
+#define ANX7483_AUX_SNOOPING_DEF 0x13
 
 /*
  * Middle Frequency Compensation
@@ -146,17 +146,17 @@
  * 5:3 UTX1_EQ_MFR CTLE middle-freq resistance when input
  * 2:0 UTX1_EQ_MFC CTLE middle-freq Capacitance
  */
-#define ANX7483_UTX1_PORT_CFG1_REG	0x53
-#define ANX7483_UTX2_PORT_CFG1_REG	0x17
-#define ANX7483_URX1_PORT_CFG1_REG	0x3F
-#define ANX7483_URX2_PORT_CFG1_REG	0x2B
-#define ANX7483_DRX1_PORT_CFG1_REG	0x5D
-#define ANX7483_DRX2_PORT_CFG1_REG	0x21
+#define ANX7483_UTX1_PORT_CFG1_REG 0x53
+#define ANX7483_UTX2_PORT_CFG1_REG 0x17
+#define ANX7483_URX1_PORT_CFG1_REG 0x3F
+#define ANX7483_URX2_PORT_CFG1_REG 0x2B
+#define ANX7483_DRX1_PORT_CFG1_REG 0x5D
+#define ANX7483_DRX2_PORT_CFG1_REG 0x21
 
 /*
  * Default CFG1 setting: current bias max, Middle frequency resistance of 0x5,
  * Middle frequency capacitance of 0x6
  */
-#define ANX7483_CFG1_DEF		0xEE
+#define ANX7483_CFG1_DEF 0xEE
 
 #endif /* __CROS_EC_USB_RETIMER_ANX7483_H */