diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-01 14:52:12 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-02 18:56:37 -0700 |
| commit | ac9f0f37362901f2418d1059ad583405e20ce65c (patch) | |
| tree | d0e3b739d88e35259bcc9d707dae81146c8e1814 /include/config_std_internal_flash.h | |
| parent | 2b5acbc8135ab49c5a10344f5d134153f52c4d17 (diff) | |
| download | chrome-ec-ac9f0f37362901f2418d1059ad583405e20ce65c.tar.gz | |
cleanup: Clarify use of flash layout CONFIGs
Based on feedback from programmers, it's not clear when
config_std_internal_flash should be used, and when non-standard
chip-specific layouts need to be defined. Add clarity here with the
following changes:
- Explain in-depth the one config that config_std_internal_flash should
be used for.
- Move non-standard chip-level flash layout CONFIGs to their own new
chip-level file, config_flash_layout. All chips should either include
config_std_internal_flash.h OR define their own layout in their own
config_flash_layout.
Functionally, this change is a NOP.
BUG=chrome-os-partner:23796
TEST=`make buildall -j`
BRANCH=None
Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296527
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'include/config_std_internal_flash.h')
| -rw-r--r-- | include/config_std_internal_flash.h | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h index d918e8a813..10cd5baf5c 100644 --- a/include/config_std_internal_flash.h +++ b/include/config_std_internal_flash.h @@ -11,9 +11,31 @@ * - RO image starts at the beginning of flash. * - PSTATE immediately follows the RO image. * - RW image starts at the second half of flash. - * - WP region consists of the first half of flash (RO + PSTATE). + * - Protected region consists of the first half of flash (RO image + PSTATE). + * - Unprotected region consists of second half of flash (RW image). + * + * PSTATE + * | + * v + * |<-----Protected Region------>|<------Unprotected Region----->| + * |<--------RO image--------->| |<----------RW image----------->| + * 0 N/2 N + * + * This layout is used by several supported chips. Chips which do not use + * this layout MUST NOT include this header file, and must instead define + * the configs below in a chip-level header file (config_flash_layout.h). + * + * See the following page for additional image geometry discussion: + * + * https://www.chromium.org/chromium-os/ec-development/ec-image-geometry-spec + * + * TODO(crosbug.com/p/23796): Finish implementing the spec. */ +/* Memory-mapped internal flash w/ PSTATE */ +#define CONFIG_FLASH_MAPPED +#define CONFIG_FLASH_PSTATE + /* * The EC uses the one bank of flash to emulate a SPI-like write protect * register with persistent state. |