diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-04-26 14:49:26 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-05-09 23:20:11 -0700 |
| commit | 375b60776156036ef458069c408e5ed4b24692f0 (patch) | |
| tree | 63b2b33aae9e74061f4a4db43adcc6426c8879f0 /include/gpio.h | |
| parent | 53b72194cdfdcdce50b5484ba0b06c2357fcc0b7 (diff) | |
| download | chrome-ec-375b60776156036ef458069c408e5ed4b24692f0.tar.gz | |
npcx: system: Add support for npcx7 series ec
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'include/gpio.h')
| -rw-r--r-- | include/gpio.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/gpio.h b/include/gpio.h index 8e6fd19444..35f53801de 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -32,6 +32,7 @@ #define GPIO_SEL_1P8V (1 << 16) /* Support 1.8v */ #define GPIO_ALTERNATE (1 << 17) /* GPIO used for alternate function. */ #define GPIO_LOCKED (1 << 18) /* Lock GPIO output and configuration */ +#define GPIO_HIB_WAKE_HIGH (1 << 19) /* Hibernate wake on high level */ /* Common flag combinations */ #define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) |