ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 105 deletions

diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h
deleted file mode 100644
index 303db20de7..0000000000
--- a/include/power/intel_x86.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Intel X86 chipset power control module for Chrome EC */
-
-
-#ifndef __CROS_EC_INTEL_X86_H
-#define __CROS_EC_INTEL_X86_H
-
-#include "espi.h"
-#include "power.h"
-
-/* Chipset specific header files */
-#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)
-#include "alderlake_slg4bd44540.h"
-/* Geminilake and apollolake use same power sequencing. */
-#elif defined(CONFIG_CHIPSET_APL_GLK)
-#include "apollolake.h"
-#elif defined(CONFIG_CHIPSET_CANNONLAKE)
-#include "cannonlake.h"
-#elif defined(CONFIG_CHIPSET_COMETLAKE)
-#include "cometlake.h"
-#elif defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE)
-#include "cometlake-discrete.h"
-#elif defined(CONFIG_CHIPSET_ICELAKE)
-#include "icelake.h"
-#elif defined(CONFIG_CHIPSET_SKYLAKE)
-#include "skylake.h"
-#endif
-
-/* GPIO for power signal */
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define SLP_S3_SIGNAL_L VW_SLP_S3_L
-#else
-#define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L
-#endif
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define SLP_S4_SIGNAL_L VW_SLP_S4_L
-#else
-#define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L
-#endif
-
-/**
- * Handle RSMRST signal.
- *
- * @param state Current chipset state.
- */
-void common_intel_x86_handle_rsmrst(enum power_state state);
-
-/**
- * Force chipset to G3 state.
- *
- * @return power_state New chipset state.
- */
-enum power_state chipset_force_g3(void);
-
-/**
- * Handle power states.
- *
- * @param state        Current chipset state.
- * @return power_state New chipset state.
- */
-enum power_state common_intel_x86_power_handle_state(enum power_state state);
-
-/**
- * Wait for power-up to be allowed based on available power.
- *
- * This delays G3->S5 until there is enough power to boot the AP, waiting
- * first until the charger (if any) is ready, then for there to be sufficient
- * power.
- *
- * In case of error, the caller should not allow power-up past G3.
- *
- * @return EC_SUCCESS if OK.
- */
-enum ec_error_list intel_x86_wait_power_up_ok(void);
-
-/**
- * Get the value of PG_EC_DSW_PWROK.
- *
- * The default implementation is just to return the GPIO.  But if a
- * board doesn't have that GPIO, they may override this function.
- */
-__override_proto int intel_x86_get_pg_ec_dsw_pwrok(void);
-
-/**
- * Get the value of PG_EC_ALL_SYS_PWRGD.
- *
- * The default implementation is just to return the GPIO.  But if a
- * board doesn't have that GPIO, they may override this function.
- */
-__override_proto int intel_x86_get_pg_ec_all_sys_pwrgd(void);
-
-/**
- * Introduces SYS_RESET_L Debounce time delay
- *
- * The default implementation is to wait for a duration of 32 ms.
- * If board needs a different debounce time delay, they may override
- * this function
- */
-__override_proto void intel_x86_sys_reset_delay(void);
-
-#endif /* __CROS_EC_INTEL_X86_H */