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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /include/power/skylake.h
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-release-R102-14695.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'include/power/skylake.h')
-rw-r--r--include/power/skylake.h57
1 files changed, 0 insertions, 57 deletions
diff --git a/include/power/skylake.h b/include/power/skylake.h
deleted file mode 100644
index c8a656c6c5..0000000000
--- a/include/power/skylake.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */
-
-#ifndef __CROS_EC_SKYLAKE_H
-#define __CROS_EC_SKYLAKE_H
-
-/*
- * Input state flags.
- * TODO: Normalize the power signal masks from board defines to SoC headers.
- */
-#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
- IN_PCH_SLP_S4_DEASSERTED | \
- IN_PCH_SLP_SUS_DEASSERTED)
-
-/*
- * DPWROK is NC / stuffing option on initial boards.
- * TODO(shawnn): Figure out proper control signals.
- */
-#define IN_PGOOD_ALL_CORE 0
-
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
-
-#define CHARGER_INITIALIZED_DELAY_MS 100
-#define CHARGER_INITIALIZED_TRIES 40
-
-/* Power signals list */
-enum power_signal {
-#ifdef CONFIG_POWER_S0IX
- X86_SLP_S0_DEASSERTED,
-#endif
- X86_SLP_S3_DEASSERTED,
- X86_SLP_S4_DEASSERTED,
- X86_SLP_SUS_DEASSERTED,
- X86_RSMRST_L_PWRGD,
- X86_PMIC_DPWROK,
-
- /* Number of X86 signals */
- POWER_SIGNAL_COUNT
-};
-
-/*
- * Board can define this function to indicate to the skylake
- * power code that it does not have working reset flags.
- */
-int board_has_working_reset_flags(void);
-
-#endif /* __CROS_EC_SKYLAKE_H */