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author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
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committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /include/spi_flash_reg.h | |
parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
download | chrome-ec-stabilize-14682.B-ish.tar.gz |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'include/spi_flash_reg.h')
-rw-r--r-- | include/spi_flash_reg.h | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h deleted file mode 100644 index a0ffefc721..0000000000 --- a/include/spi_flash_reg.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI flash protection register translation functions for Chrome OS EC. - */ - -#ifndef __CROS_EC_SPI_FLASH_REG_H -#define __CROS_EC_SPI_FLASH_REG_H - -#include "common.h" - -/* - * Common register bits for SPI flash. All registers / bits may not be valid - * for all parts. - */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) - -/* SR2 register existence based upon chip */ -#ifdef CONFIG_SPI_FLASH_W25X40 -#undef CONFIG_SPI_FLASH_HAS_SR2 -#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B) -#define CONFIG_SPI_FLASH_HAS_SR2 -#endif - -/* W25Q128 16 Mbyte SPI flash for testing */ -#ifdef CONFIG_SPI_FLASH_W25Q128 -#define CONFIG_SPI_FLASH_HAS_SR2 -#endif - -/** - * Computes block write protection range from registers - * Returns start == len == 0 for no protection - * - * @param sr1 Status register 1 - * @param sr2 Status register 2 - * @param start Output pointer for protection start offset - * @param len Output pointer for protection length - * - * @return EC_SUCCESS, or non-zero if any error. - */ -int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start, - unsigned int *len); - -/** - * Computes block write protection registers from range - * - * @param start Desired protection start offset - * @param len Desired protection length - * @param sr1 Output pointer for status register 1 - * @param sr2 Output pointer for status register 2 - * - * @return EC_SUCCESS, or non-zero if any error. - */ -int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1, - uint8_t *sr2); - -#endif /* __CROS_EC_SPI_FLASH_REG_H */ |