Add the functions to read and write EAR.

EAR (extended address register) is used to access addresses above
16MiB when 3-byte address mode is used. These two functions allow to
write to and read from EAR to set up what addresses to access in
3-byte mode. For example, for a 64MiB EEPROM:

EAR value                       Addresses to access
  0                            0x0000000 - 0x0FFFFFF
  1                            0x1000000 - 0x1FFFFFF
  2                            0x2000000 - 0x2FFFFFF
  3                            0x3000000 - 0x3FFFFFF

BUG=b:132252340
BRANCH=none
TEST=manual

Testing:
1. Writing to EAR returns successfully.
2. Writing different values to EAR, verify that accessing EERPOM
in 3-byte mode is to the correct address, e.g., when EAR=2,
accessing 0x0FFFFFF is actually to 0x2FFFFFF.

Change-Id: I2a8bde7fc4b9069afc80a81042fb47359bffa015
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688150
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Pai Peng <paipeng@google.com>
Commit-Queue: Pai Peng <paipeng@google.com>

1 files changed, 23 insertions, 11 deletions

diff --git a/include/spi_nor.h b/include/spi_nor.h
index 4bf8d853f2..77347399d7 100644
--- a/include/spi_nor.h
+++ b/include/spi_nor.h
@@ -61,16 +61,18 @@ extern const unsigned int spi_nor_devices_used;
 
 /* Industry standard Serial NOR Flash opcodes. All other opcodes are part
  * specific and require SFDP discovery. */
-#define SPI_NOR_OPCODE_WRITE_STATUS 0x01   /* Write Status Register (1 Byte) */
-#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02   /* Page program */
-#define SPI_NOR_OPCODE_SLOW_READ 0x03      /* Read data (low frequency) */
+#define SPI_NOR_OPCODE_WRITE_STATUS  0x01 /* Write Status Register (1 Byte) */
+#define SPI_NOR_OPCODE_PAGE_PROGRAM  0x02 /* Page program */
+#define SPI_NOR_OPCODE_SLOW_READ     0x03 /* Read data (low frequency) */
 #define SPI_NOR_OPCODE_WRITE_DISABLE 0x04
-#define SPI_NOR_OPCODE_READ_STATUS 0x05    /* Read Status Register */
-#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06
-#define SPI_NOR_OPCODE_FAST_READ 0x0b      /* Read data (high frequency) */
-#define SPI_NOR_OPCODE_SFDP 0x5a           /* Read JEDEC SFDP */
-#define SPI_NOR_OPCODE_JEDEC_ID 0x9f       /* Read JEDEC ID */
-#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7     /* Erase whole flash chip */
+#define SPI_NOR_OPCODE_READ_STATUS   0x05 /* Read Status Register */
+#define SPI_NOR_OPCODE_WRITE_ENABLE  0x06
+#define SPI_NOR_OPCODE_FAST_READ     0x0b /* Read data (high frequency) */
+#define SPI_NOR_OPCODE_SFDP          0x5a /* Read JEDEC SFDP */
+#define SPI_NOR_OPCODE_JEDEC_ID      0x9f /* Read JEDEC ID */
+#define SPI_NOR_OPCODE_WREAR         0xc5 /* Write extended address register */
+#define SPI_NOR_OPCODE_CHIP_ERASE    0xc7 /* Erase whole flash chip */
+#define SPI_NOR_OPCODE_RDEAR         0xc8 /* Read extended address register */
 
 /* Flags for SPI_NOR_OPCODE_READ_STATUS */
 #define SPI_NOR_STATUS_REGISTER_WIP BIT(0)  /* Write in progres */
@@ -78,13 +80,13 @@ extern const unsigned int spi_nor_devices_used;
 
 /* If needed in the future this driver can be extended to discover SFDP
  * advertised erase sizes and opcodes for SFDP v1.0+. */
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20
+#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE  0x20
 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8
 
 /* If needed in the future this driver can be extended to discover 4B entry and
  * exit methods for SFDP v1.5+. */
 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9
+#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B  0xe9
 
 /* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */
 #define SPI_NOR_JEDEC_ID_BANKS 12
@@ -168,4 +170,14 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 		  uint32_t offset, size_t size, const uint8_t *data);
 
+/**
+ * Write to the extended address register.
+ * @param  spi_nor_device The Serial NOR Flash device to use.
+ * @param  value          The value to write.
+ * @return                ec_error_list (non-zero on error and timeout).
+ */
+int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
+		      const uint8_t value);
+
+
 #endif  /* __CROS_EC_SPI_NOR_H */