diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 15:15:58 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-28 15:52:40 +0000 |
| commit | fc6b1da8bf485f435689ceace395ac0cb2762eb5 (patch) | |
| tree | 3e6fdd255c13320d27372b501b1bb4ba0dd63de9 /include | |
| parent | 13888e395e6ef44d2201a6f7ffbe705a7a124d82 (diff) | |
| download | chrome-ec-fc6b1da8bf485f435689ceace395ac0cb2762eb5.tar.gz | |
include/spi_flash_reg.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: Ieca7f0ee9dd8b4a443c177539ec656846d9e536c
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730409
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/spi_flash_reg.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h index a0ffefc721..46e8ee20d6 100644 --- a/include/spi_flash_reg.h +++ b/include/spi_flash_reg.h @@ -15,21 +15,21 @@ * Common register bits for SPI flash. All registers / bits may not be valid * for all parts. */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* SR2 register existence based upon chip */ #ifdef CONFIG_SPI_FLASH_W25X40 @@ -70,4 +70,4 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start, int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1, uint8_t *sr2); -#endif /* __CROS_EC_SPI_FLASH_REG_H */ +#endif /* __CROS_EC_SPI_FLASH_REG_H */ |