ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

1 files changed, 0 insertions, 277 deletions

diff --git a/power/alderlake_slg4bd44540.c b/power/alderlake_slg4bd44540.c
deleted file mode 100644
index e7ae9497a2..0000000000
--- a/power/alderlake_slg4bd44540.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This was originally copied form power/icelake.c (also used on TGL and
- * ADL) and adapted to support ADL designs using the Silergy SLG4BD44540
- * power sequencer chip.
- */
-
-#include "board_config.h"
-#include "chipset.h"
-#include "console.h"
-#include "gpio.h"
-#include "power.h"
-#include "power/alderlake_slg4bd44540.h"
-#include "power/intel_x86.h"
-#include "timer.h"
-
-/*
- * These delays are used by the brya power sequence reference design and
- * should be suitable for variants.
- */
-
-/* SEQ_EC_ALL_SYS_PG high to VCCST_PWRGD high delay */
-#define VCCST_PWRGD_DELAY_MS	2
-
-/* IMVP9_VRRDY high to PCH_PWROK high delay */
-#define PCH_PWROK_DELAY_MS	2
-
-/* SEQ_EC_ALL_SYS_PG high to EC_PCH_SYS_PWROK high delay */
-#define SYS_PWROK_DELAY_MS	45
-
-/* IMVP9_VRRDY high timeout */
-#define VRRDY_TIMEOUT_MS	50
-
-/* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-#ifdef CONFIG_BRINGUP
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level_verbose(CC_CHIPSET, signal, value)
-#else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
-#endif
-
-/* The wait time is ~150 msec, allow for safety margin. */
-#define IN_PCH_SLP_SUS_WAIT_TIME_USEC	(250 * MSEC)
-
-/* Power signals list. Must match order of enum power_signal. */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_DEASSERTED] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH |
-			POWER_SIGNAL_DISABLE_AT_BOOT,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_DEASSERTED] = {
-		.gpio = SLP_S3_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S4_DEASSERTED] = {
-		.gpio = SLP_S4_SIGNAL_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S4_DEASSERTED",
-	},
-	[X86_SLP_SUS_DEASSERTED] = {
-		.gpio = GPIO_SLP_SUS_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_SUS_DEASSERTED",
-	},
-	[X86_RSMRST_L_PGOOD] = {
-		.gpio = GPIO_PG_EC_RSMRST_ODL,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "RSMRST_L_PGOOD",
-	},
-	[X86_DSW_DPWROK] = {
-		.gpio = GPIO_PG_EC_DSW_PWROK,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "DSW_DPWROK",
-	},
-	[X86_ALL_SYS_PGOOD] = {
-		.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "ALL_SYS_PWRGD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-__overridable int intel_x86_get_pg_ec_dsw_pwrok(void)
-{
-	return gpio_get_level(GPIO_PG_EC_DSW_PWROK);
-}
-
-__overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void)
-{
-	return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
-}
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	int timeout_ms = 50;
-
-	CPRINTS("%s() %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/* Turn off RMSRST_L  to meet tPCH12 */
-	board_before_rsmrst(0);
-	GPIO_SET_LEVEL(GPIO_PCH_RSMRST_L, 0);
-	board_after_rsmrst(0);
-
-	/* Turn off S5 rails */
-	GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 0);
-
-	/*
-	 * TODO(b/179519791): Replace this wait with
-	 * power_wait_signals_timeout()
-	 */
-	/* Now wait for DSW_PWROK and  RSMRST_ODL to go away. */
-	while (intel_x86_get_pg_ec_dsw_pwrok() &&
-	       gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) {
-		msleep(1);
-		timeout_ms--;
-	};
-
-	if (!timeout_ms)
-		CPRINTS("DSW_PWROK or RSMRST_ODL didn't go low!  Assuming G3.");
-}
-
-void chipset_handle_espi_reset_assert(void)
-{
-	/* No special handling needed. */
-}
-
-enum power_state chipset_force_g3(void)
-{
-	chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
-
-	return POWER_G3;
-}
-
-static void ap_off(void)
-{
-	GPIO_SET_LEVEL(GPIO_VCCST_PWRGD_OD, 0);
-	GPIO_SET_LEVEL(GPIO_PCH_PWROK, 0);
-	GPIO_SET_LEVEL(GPIO_EC_PCH_SYS_PWROK, 0);
-}
-
-/*
- * We have asserted VCCST_PWRGO_OD, now wait for the IMVP9.1
- * to assert IMVP9_VRRDY_OD.
- *
- * Returns state of VRRDY.
- */
-
-static int wait_for_vrrdy(void)
-{
-	int timeout_ms = VRRDY_TIMEOUT_MS;
-	int vrrdy;
-
-	for (; timeout_ms > 0; --timeout_ms) {
-		vrrdy = gpio_get_level(GPIO_IMVP9_VRRDY_OD);
-		if (vrrdy != 0)
-			return 1;
-		msleep(1);
-	}
-	return 0;
-}
-
-/*
- * The relationship between these signals is described in
- * Intel PDG #627205 rev. 0.81.
- *
- * tCPU16: >= 0
- *	VCCST_PWRGD to PCH_PWROK
- * tPLT05: >= 0
- *	SYS_ALL_PWRGD to SYS_PWROK
- *	PCH_PWROK to SYS_PWROK
- */
-
-static void all_sys_pwrgd_pass_thru(void)
-{
-	int sys_pg;
-	int vccst_pg;
-	int pch_pok;
-	int sys_pok;
-
-	sys_pg = gpio_get_level(GPIO_SEQ_EC_ALL_SYS_PG);
-
-	if (IS_ENABLED(CONFIG_BRINGUP))
-		CPRINTS("SEQ_EC_ALL_SYS_PG is %d", sys_pg);
-
-	if (sys_pg == 0) {
-		ap_off();
-		return;
-	}
-
-	/* SEQ_EC_ALL_SYS_PG is asserted, enable VCCST_PWRGD_OD. */
-
-	vccst_pg = gpio_get_level(GPIO_VCCST_PWRGD_OD);
-	if (vccst_pg == 0) {
-		msleep(VCCST_PWRGD_DELAY_MS);
-		GPIO_SET_LEVEL(GPIO_VCCST_PWRGD_OD, 1);
-	}
-
-	/* Enable PCH_PWROK, gated by VRRDY. */
-
-	pch_pok = gpio_get_level(GPIO_PCH_PWROK);
-	if (pch_pok == 0) {
-		if (wait_for_vrrdy() == 0) {
-			CPRINTS("Timed out waiting for VRRDY, "
-				"shutting AP off!");
-			ap_off();
-			return;
-		}
-		msleep(PCH_PWROK_DELAY_MS);
-		GPIO_SET_LEVEL(GPIO_PCH_PWROK, 1);
-	}
-
-	/* Enable PCH_SYS_PWROK. */
-
-	sys_pok = gpio_get_level(GPIO_EC_PCH_SYS_PWROK);
-	if (sys_pok == 0) {
-		msleep(SYS_PWROK_DELAY_MS);
-		/* Check if we lost power while waiting. */
-		sys_pg = gpio_get_level(GPIO_SEQ_EC_ALL_SYS_PG);
-		if (sys_pg == 0) {
-			CPRINTS("SEQ_EC_ALL_SYS_PG deasserted, "
-				"shutting AP off!");
-			ap_off();
-			return;
-		}
-		GPIO_SET_LEVEL(GPIO_EC_PCH_SYS_PWROK, 1);
-		/* PCH will now release PLT_RST */
-	}
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	all_sys_pwrgd_pass_thru();
-
-	common_intel_x86_handle_rsmrst(state);
-
-	switch (state) {
-
-	case POWER_G3S5:
-		GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 1);
-
-		if (power_wait_signals(IN_PGOOD_ALL_CORE))
-			break;
-
-		/*
-		 * Now wait for SLP_SUS_L to go high based on tPCH32. If this
-		 * signal doesn't go high within 250 msec then go back to G3.
-		 */
-		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
-				IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
-			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
-			return POWER_S5G3;
-		}
-		break;
-
-	case POWER_S5:
-		/* If SLP_SUS_L is asserted, we're no longer in S5. */
-		if (!power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
-			return POWER_S5G3;
-		break;
-
-	default:
-		break;
-	}
-
-	return common_intel_x86_power_handle_state(state);
-}