Code cleanup: Remove cold reset logic

Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j
     Manually tested on GLKRVP, apreset EC command can reset AP.

Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>

1 files changed, 11 insertions, 30 deletions

diff --git a/power/braswell.c b/power/braswell.c
index bfdf3dec39..0b91040cbc 100644
--- a/power/braswell.c
+++ b/power/braswell.c
@@ -68,38 +68,19 @@ void chipset_force_shutdown(void)
 	forcing_shutdown = 1;
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
-	if (cold_reset) {
-		/*
-		 * Drop and restore PWROK.  This causes the PCH to reboot,
-		 * regardless of its after-G3 setting.  This type of reboot
-		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
-		 * we actually drop power to the rest of the system (hence, a
-		 * "cold" reboot).
-		 */
-
-		/* Ignore if PWROK is already low */
-		if (gpio_get_level(GPIO_PCH_SYS_PWROK) == 0)
-			return;
-
-		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-		udelay(100);
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
+	CPRINTS("%s", __func__);
 
-	} else {
-		/*
-		 * Send a reset pulse to the PCH.  This just causes it to
-		 * assert INIT# to the CPU without dropping power or asserting
-		 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-		 * ms debounce time, so assert the signal for twice that.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		usleep(32 * MSEC);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
+	/*
+	 * Send a reset pulse to the PCH.  This just causes it to
+	 * assert INIT# to the CPU without dropping power or asserting
+	 * PLTRST# to reset the rest of the system.  The PCH uses a 16
+	 * ms debounce time, so assert the signal for twice that.
+	 */
+	gpio_set_level(GPIO_PCH_RCIN_L, 0);
+	usleep(32 * MSEC);
+	gpio_set_level(GPIO_PCH_RCIN_L, 1);
 }
 
 void chipset_throttle_cpu(int throttle)