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author | Aseda Aboagye <aaboagye@google.com> | 2018-06-07 18:00:20 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-08 16:14:14 -0700 |
commit | f39c9fb0466ab5729aeba13ec4a52079d561f03b (patch) | |
tree | 89bb1670b6294192801b236bbefc64577b254ebc /power/braswell.c | |
parent | 3846871131d40790efcc9467eb3cfa01b859969e (diff) | |
download | chrome-ec-f39c9fb0466ab5729aeba13ec4a52079d561f03b.tar.gz |
power: Add CONFIG_* option for PROCHOT polarity.
The common x86 chipset code assumed that CPU_PROCHOT was active high,
however on some boards it's actually active low. This commit simply
adds a CONFIG_* option, CONFIG_CPU_PROCHOT_IS_ACTIVE_LOW, and inverts
the places where the signal is used.
BUG=b:109882953
BRANCH=poppy
TEST=Enable on nocturne; flash, verify that CPU_PROCHOT is not asserted
by default.
Change-Id: I6d871e4979b79333cf4897d77c995eadbb34fd43
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1092150
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'power/braswell.c')
-rw-r--r-- | power/braswell.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/power/braswell.c b/power/braswell.c index 0b91040cbc..e04918c055 100644 --- a/power/braswell.c +++ b/power/braswell.c @@ -85,6 +85,9 @@ void chipset_reset(void) void chipset_throttle_cpu(int throttle) { +#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW + throttle = !throttle; +#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */ if (chipset_in_state(CHIPSET_STATE_ON)) gpio_set_level(GPIO_CPU_PROCHOT, throttle); } @@ -204,7 +207,11 @@ enum power_state power_handle_state(enum power_state state) * Throttle CPU if necessary. This should only be asserted * when +VCCP is powered (it is by now). */ +#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW + gpio_set_level(GPIO_CPU_PROCHOT, !throttle_cpu); +#else gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu); +#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */ /* Set SYS and CORE PWROK */ gpio_set_level(GPIO_PCH_SYS_PWROK, 1); |