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| author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-17 13:56:46 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-10-26 01:44:08 -0700 |
| commit | 5cfa02b03c2b90918fbbb238ab736758bd601281 (patch) | |
| tree | dc6e818d6d2f2e1518c7726059dfdaedc320669d /power/skylake.c | |
| parent | b142b05465052511b837ac71ab079081ff9430ae (diff) | |
| download | chrome-ec-5cfa02b03c2b90918fbbb238ab736758bd601281.tar.gz | |
lpc: Add function for host reset without RCIN GPIO
Prior x86 boards have had GPIO for toggling RCIN directly on the PCH,
although many likely had HW-assisted methods as well.
With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality
software control over RCIN Virtual Wire is not available with the npcx EC,
so the legacy LPC interface for pulsing KBRST must be used instead as this
is the only way to generate RCIN.
This method will likely vary on different EC chips, but for skylake it
can just be abstracted into the LPC module.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=successful 'apreset warm' on eve EC console
Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400037
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power/skylake.c')
| -rw-r--r-- | power/skylake.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/power/skylake.c b/power/skylake.c index 7ac5146d93..718ff5aeca 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -131,9 +131,13 @@ void chipset_reset(int cold_reset) */ /* Pulse must be at least 16 PCI clocks long = 500 ns */ +#ifdef CONFIG_ESPI_VW_SIGNALS + lpc_host_reset(); +#else gpio_set_level(GPIO_PCH_RCIN_L, 0); udelay(10); gpio_set_level(GPIO_PCH_RCIN_L, 1); +#endif } } |