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authorShamile Khan <shamile.khan@intel.com>2017-10-25 12:53:13 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-01-16 21:26:27 -0800
commit0348eb1059cd4fa43b8426013314f76ac201bd7a (patch)
tree824bc8359a252fbb962a4b4a05b9fd08f266b04a /power
parent51e9e69f386366256807e6f4ccdd258821cdcfe0 (diff)
downloadchrome-ec-0348eb1059cd4fa43b8426013314f76ac201bd7a.tar.gz
glkrvp: Enable eSPI instead of LPC including eSPI VW based SCI/SMI
BUG=None BRANCH=None TEST=GLKRVP can boot to OS when a coreboot image with eSPI enabled is flashed. Change-Id: Ia534bdbbe517c53ba2e0beafc41b421872f1e33d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/818196 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power')
-rw-r--r--power/apollolake.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/power/apollolake.c b/power/apollolake.c
index c3ca7f55f5..feecd24f8e 100644
--- a/power/apollolake.c
+++ b/power/apollolake.c
@@ -42,6 +42,10 @@ enum power_state chipset_force_g3(void)
return POWER_G3;
}
+void chipset_handle_espi_reset_assert(void)
+{
+}
+
void chipset_reset(int cold_reset)
{
CPRINTS("%s(%d)", __func__, cold_reset);