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| author | Aseda Aboagye <aaboagye@google.com> | 2022-04-01 12:36:33 -0500 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-01 21:52:43 +0000 |
| commit | 6700cb3825b822793d8de3c69f1c7a513c27280e (patch) | |
| tree | d450f04acf76ab5a9dcdac8682e275d05f84152e /power | |
| parent | caf06d733d84975a91eb5b331678be04b5ac18aa (diff) | |
| download | chrome-ec-6700cb3825b822793d8de3c69f1c7a513c27280e.tar.gz | |
jsl: Kick chipset SM if power loss in suspend
On the jasperlake platforms, our DSW_PWROK is actually generated by the
EC but it relies on the ADC interrupts to be enabled. For power
reasons, we do not keep the ADC interrupts enabled during suspend as the
assumption is that the power rails will not be lost. However, it seems
that that may actually occur. This would cause the chipset state machine
to be stuck in suspend when the system is actually no longer in suspend.
This commit simply has the EC do a couple of things:
- In suspend, assume that the PP3300_A power good follows the enable
- During a force shutdown, manually trigger the chipset state machine to
re-evaluate the current signals.
BUG=b:218596390
BRANCH=firmware-dedede-13606.B
TEST=Build and flash magolor, login as guest, close lid, wait for system
to enter S0ix. Issue `apshutdown` on EC console, verify that DUT enters
S5 and G3. Open lid, verify that DUT boots back to S0.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I2e104857851f245bf37574a8a47e415633fb9e77
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3566111
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Feels: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/icelake.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/power/icelake.c b/power/icelake.c index f06c116897..00248061e9 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -120,6 +120,15 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) GPIO_SET_LEVEL(GPIO_EN_PP5000, 0); /* + * For JSL, we may not catch the DSW power good transitioning if this + * occurs in suspend as our ADC interrupts are disabled for power + * reasons. Therefore, kick the chipset state machine in order to catch + * up with the current state of affairs. + */ + if (IS_ENABLED(CONFIG_CHIPSET_JASPERLAKE)) + power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); + + /* * TODO(b/111810925): Replace this wait with * power_wait_signals_timeout() */ |