zephyr: volteer: update header information using Kconfig

Make npcx builds done by zephyr have valid format, this means:
1. Only the first section (RO) should have the header.
2. The header should use the chip information or add new Kconfig
   values if needed.
3. This should not be done per board (one centralized place).

Move the cmake logic to generate the header via ecst.py script (
located in the zephyr repository and is used to generate the header
for the npcx chips) to a common place: zephyr/CMakeLists.txt. With
that change, the board-specific CMakeLists.txt is now removed, to
be replaced with a call to set ECST_CHIP_ARG. This value must be
set because zephyr only defines SOC_NPCX7M6FB while our specific chip
 is different.

For the same reason, both volteer and kohaku require overriding
zephyr's default CONFIG_FLASH_SIZE for the npcx7m6fb.

Additionally, each build (RO/RW) will no longer generate the final
output using the board's name. This will help zmake find the image
with the header without requiring additional arguments.

BRANCH=none
BUG=b:164421798
TEST=build volteer, flash the joined binary, see it boot
TEST=build kohaku

Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I418c138e33812c411503f8260fdaa85059a737c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682173
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>

1 files changed, 56 insertions, 3 deletions

diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header
index 16a03dfab0..da57ad24b7 100644
--- a/zephyr/Kconfig.header
+++ b/zephyr/Kconfig.header
@@ -5,6 +5,8 @@
 config PLATFORM_EC_RO_HEADER
 	bool "RO section includes a header"
 	default y
+	depends on CROS_EC_RO
+	depends on SOC_FAMILY_NPCX
 	help
 	  The RO image residing on flash memory has a header section. The header
 	  is used on some chips (such as the npcx) to load the image correctly
@@ -12,8 +14,6 @@ config PLATFORM_EC_RO_HEADER
 	  scripts to generate the header. See core/cortex-m/ec.lds.S for
 	  reference.
 
-if PLATFORM_EC_RO_HEADER
-
 config PLATFORM_EC_RO_HEADER_OFFSET
 	hex "Offset in memory for the location of the header"
 	default 0x0
@@ -28,4 +28,57 @@ config PLATFORM_EC_RO_HEADER_SIZE
 	  The size of the RO header in bytes. This values should come from the
 	  datasheet of the chip being used.
 
-endif # PLATFORM_EC_RO_HEADER
\ No newline at end of file
+config PLATFORM_EC_RO_HEADER_ENABLE_HEADER_CRC
+	bool "Enable header crc check"
+	help
+	  When enabled, the header will be verified at boot using a crc
+	  checksum.
+
+config PLATFORM_EC_RO_HEADER_ENABLE_FIRMWARE_CRC
+	bool "Enable firmware image crc check"
+	help
+	  When enabled, the firmware image will be verified at boot using a
+	  crc checksum.
+
+choice "SPI flash max clock rate"
+	prompt "Clock rate to use for SPI flash"
+	help
+	  This selects the max clock rate (one of 20, 25, 33, 40, or 50 MHz)
+	  that will be used for the SPI flash.
+
+config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_20
+	bool "SPI flash max clock rate of 20 MHz"
+
+config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_25
+	bool "SPI flash max clock rate of 25 MHz"
+
+config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_33
+	bool "SPI flash max clock rate of 33 MHz"
+
+config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_40
+	bool "SPI flash max clock rate of 40 MHz"
+
+config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50
+	bool "SPI flash max clock rate of 50 MHz"
+
+endchoice # SPI flash max clock rate
+
+choice "SPI flash reading mode"
+	prompt "Reading mode used by the SPI flash"
+	help
+	  This will set the reading mode that can be used by the SPI flash.
+	  Reading modes supported are normal, fast, dual, and quad.
+
+config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_NORMAL
+	bool "SPI flash will operate with normal reading mode"
+
+config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_FAST
+	bool "SPI flash will operate with fast reading mode"
+
+config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL
+	bool "SPI flash will operate with dual reading mode"
+
+config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_QUAD
+	bool "SPI flash will operate with quad reading mode"
+
+endchoice # SPI flash reading mode