diff options
author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
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committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | |
parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
download | chrome-ec-stabilize-14588.123.B-ish.tar.gz |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9')
-rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 deleted file mode 100644 index 5fd1fbd308..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the correct defaults when using the NPCX9 series chipset -# - -if SOC_SERIES_NPCX9 - -# -# NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM -# NPCX996F: 512 KiB Flash, 192 KiB code RAM, 64 KiB data RAM -# - -# Code RAM base for NPCX9 series -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10080000 if SOC_NPCX9M3F - default 0x10090000 if SOC_NPCX9M6F - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x0000f800 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 512 - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# NPCX993F: Image size limited by 1/2 Flash size (256 KiB) and -# code RAM size (256 KiB) -# NPCX996F: Image size limited by code RAM size (192 KiB) - -config CROS_EC_RO_SIZE - default 0x40000 if SOC_NPCX9M3F - default 0x30000 if SOC_NPCX9M6F - -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x40000 if SOC_NPCX9M3F - default 0x30000 if SOC_NPCX9M6F - -endif # SOC_SERIES_NPCX9 |