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authorJack Rosenthal <jrosenth@chromium.org>2021-11-04 12:11:58 -0600
committerCommit Bot <commit-bot@chromium.org>2021-11-05 04:22:34 +0000
commit252457d4b21f46889eebad61d4c0a65331919cec (patch)
tree01856c4d31d710b20e85a74c8d7b5836e35c3b98 /zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
parent08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff)
downloadchrome-ec-stabilize-14345.B-ish.tar.gz
In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2')
-rw-r--r--zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx241
1 files changed, 0 insertions, 41 deletions
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
deleted file mode 100644
index dab9e6b8b2..0000000000
--- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
+++ /dev/null
@@ -1,41 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-if SOC_FAMILY_RISCV_ITE
-
-# Code RAM base for IT8XXX2
-config CROS_EC_PROGRAM_MEMORY_BASE
- default 0x80000000
-
-# The total RAM size of IT8xxx2 is 60 KB.
-# The first 4KB block be always reserved for ram code functions,
-# so the total available RAM size will be 56KB.
-config CROS_EC_RAM_BASE
- default 0x80101000
-
-config CROS_EC_DATA_RAM_SIZE
- default 0x0000e000
-
-config CROS_EC_RAM_SIZE
- default 0x0000e000
-
-# The 512KB flash space layout are as the below:
-# - RO image starts at the beginning of flash.
-# - RW image starts at the second half of flash.
-config CROS_EC_RO_MEM_OFF
- default 0x0
-
-config CROS_EC_RO_SIZE
- default 0x40000
-
-config CROS_EC_RW_MEM_OFF
- default 0x40000
-
-config CROS_EC_RW_SIZE
- default 0x40000
-
-config FLASH_LOAD_OFFSET
- default CROS_EC_RW_MEM_OFF if CROS_EC_RW
-
-endif # SOC_FAMILY_RISCV_ITE